Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

Efficient implementations of kernel computations

Abstract: A method and apparatus for efficiently performing digital signal processing is provided. In one embodiment, kernel matrix computations are simplified by grouping similar kernel coefficients together. Each coefficient group contains only coefficients having the same value. At least one of the coefficient groups has at least two coefficients. Techniques are disclosed herein to efficiently apply successive first order difference operations to a data signal. The techniques allow for a low gate count. In particular, the techniques allow for a reduction of the number of multipliers without increasing clock frequency, in an embodiment. The techniques update pixels of a data signal at a rate of two clock cycles per each pixel, in an embodiment. The techniques allow hardware that is used to process a first pixel to be re-used to start the processing of a second pixel while the first pixel is still being processed.

An FPGA implementation of a soft-in soft-out decoder for block codes

Abstract: This paper presents an FPGA implementation of the vector SISO algorithm for the (64, 57) extended Hamming code (EH) and (64, 51) extended Bose, Chaudhri, and Hocquenghem code (EBCH). The decoder architecture is defined in VHDL and the circuit is implemented on a Xilinx XC2VP100-1704ff-5 FPGA device. To achieve the required throughput, a pipelined data path architecture operating off a master clock was selected. To reduce gate count, the dynamic range of intermediate results was limited through use of saturation arithmetic. The decoder functionality was verified by means of a test bench that compared the decoded bit stream with error free transmitted signals. SISO decoder design choices that impact the bit error rate (BER) are also presented.

Hardware Implementation of the Compressed Beamforming Weights Calculation for the Practical Wireless MIMO-OFDM Communication System

Abstract: The compressed beamforming weights (CBWs) feedback is used in the IEEE 802.11n/ac WLAN, an example of the practical beamforming multiple input multiple output-orthogonal frequency division multiplexing system, to reduce the amount of feedback information so that the beamformee can respond rapidly to the beamformer. The CBW associated with each sub-carrier includes the quantized angles obtained from QR-decomposition (QRD) of the right singular vectors of each corresponding channel matrix. Efficient matrix QRD and singular value decomposition (SVD) together are therefore desirable for computing the CBWs associated with all sub-carriers. Considering the exemplary antenna configuration of 4 beamformer and 2 beamformee antennas, we propose to apply the same matrix triangulation to compute the SVD of a 2-by-4 matrix and to compute the QRD of a 4-by-2 matrix. We can achieve gate count reduction by exploiting only one matrix triangulation module in our architecture. The VLSI implementation results under the TSMC 90-ns CMOS technology reveal that our architecture requires 194.25K gates while operating at frequency 200.75 MHz. Additionally, with better normalized matrix throughput and gate efficiency, our architecture outperforms one earlier architectural design to compute the CBWs.

ASIC Design of Reversible Adder and Multiplier

Abstract: Reversible logic is one of the promising research areas in low power applications such as quantum computing, optical information processing and low power CMOS design. In this paper we present a reversible carry look ahead adder and an array multiplier. The circuits are designed such that they result in less garbage outputs, constant inputs, and less gate count compared to previous existing designs. We also gain better improvements in terms of power and area when compared to conventional adders and multipliers. The implemented designs are simulated using NC launch and synthesized by RTL compiler. Keywords Reversible, Garbage constant, Garbage output. 1. INTRODUCTION Power dissipation is one of the important problems faced now a day in VLSI design [4]. The combinational circuit dissipates KTlog 2 [1] Joules of heat for every bit of information to be lasted, irrespective of the technology used .where K is Boltzmann constant and T is temperature. Heat dissipation reduces the life span of the circuits. The information is lost when input bits are not able to recover from the output vectors. Reversible gates naturally take care of heat, since input vectors are uniquely recovered from the output vectors. That is there is one-to-one correspondence between input vectors and output vectors. Each output of the Reversible gates is used once, that is the Reversible circuit is feedback free. Some of the terms related to Reversible logic are [2, 3].

CORDIC on a configurable serial architecture for biomedical signal processing applications

Abstract: The CORDIC (COrdinated Rotation DIgital Computer)[1] algorithm provides an efficient and accurate platform to compute various trigonometric, linear and non-linear functions using only shift-add operations. This paper presents the implementation of CORDIC algorithm on a configurable architecture to port various transforms which forms the heart of image and signal processing applications. We shall demonstrate this through the mapping of trigonometric, hyperbolic, logarithm and exponential CORDIC functions on the proposed architecture. Furthermore, we show the benefits of the architecture in terms of configurability and cycle timing with a reduced gate count implementation.