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Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.


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Journal ArticleDOI
TL;DR: The first such tool, majority logic synthesizer, is built, on top of an existing Boolean logic synthesis tool, to lay the foundation for research on the development of synthesis methodologies and tools to generate optimized majority/minority networks for these emergent technologies.
Abstract: In this paper, we present a methodology for efficient majority/minority network synthesis of arbitrary multiout- put Boolean functions. Many emerging nanoscale technologies, such as quantum cellular automata (QCA), single electron tunneling (SET), and tunneling phase logic (TPL), are capable of implementing majority or minority logic very efficiently. The main purpose of this paper is to lay the foundation for research on the development of synthesis methodologies and tools to generate optimized majority/minority networks for these emergent technologies. Functionally correct QCA-, SET-, and TPL-based majority/ minority gates have been successfully demonstrated. However, there exists no comprehensive methodology or design automation tool for general multilevel majority/minority network synthesis. We have built the first such tool, majority logic synthesizer, on top of an existing Boolean logic synthesis tool. Experiments with 40 Microelectronics Center of North Carolina benchmarks were performed. They indicate that up to 68.0% reduction in gate count is possible when utilizing majority/minority logic, with the average reduction being 21.9%, compared to traditional logic synthesis, in which two-input and/or gates in the circuit are converted to majority/minority gates.

52 citations

Journal ArticleDOI
TL;DR: This paper focuses on the circuits composed with global Ising entangling gates and arbitrary addressable single-qubit gates and shows that under certain circumstances the use of global operations can substantially improve the entangling gate count.
Abstract: The disclosure describes various aspects of techniques for using global interactions in efficient quantum circuit constructions. More specifically, this disclosure describes ways to use a global entangling operator to efficiently implement circuitry common to a selection of important quantum algorithms. The circuits may be constructed with global Ising entangling gates (e.g., global Molmer-Sorenson gates or GMS gates) and arbitrary addressable single-qubit gates. Examples of the types of circuits that can be implemented include stabilizer circuits, Toffoli-4 gates, Toffoli-n gates, quantum Fourier transformation (QTF) circuits, and quantum Fourier adder (QFA) circuits. In certain instances, the use of global operations can substantially improve the entangling gate count.

52 citations

Journal ArticleDOI
TL;DR: Factoring techniques are incorporated in computer-oriented algorithms for the synthesis of fan-in limited NAND switching networks and tree networks with reduced gate count or levels of logic are sought.
Abstract: Factoring techniques are incorporated in computer-oriented algorithms for the synthesis of fan-in limited NAND switching networks. Tree networks with reduced gate count or levels of logic are sought. While example FORTRAN programs emphasize computer execution of the algorithms, they are also efficient for hand execution.

52 citations

Proceedings ArticleDOI
01 Jun 1996
TL;DR: A branch-and-bound algorithm with proposed lower bound functions is used to solve the presented formalization in the PEAS-I system and the experimental results show that the proposed method is found to be effective and efficient.
Abstract: This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (application specific integrated processor). The partitioning problem is formalized as a combinatorial optimization problem that partitions the operations into hardware and software so that the HW cost (gate count) of the designed pipelined ASIP is minimized under given execution cycle and power consumption constraints. A branch-and-bound algorithm with proposed lower bound functions is used to solve the presented formalization in the PEAS-I system. The experimental results show that the proposed method is found to be effective and efficient.

52 citations

Proceedings ArticleDOI
08 Sep 2003
TL;DR: All templates for m/spl les/7 are described in this paper and a transformation reducing the gate count can be applied via template matching.
Abstract: Reversible logic functions can be realized as networks of Toffoli gates. The synthesis of Toffoli networks can be divided into two steps. First, find a network that realizes the desired function. Second, transform the network such that it uses fewer gates, while realizing the same function. This paper addresses the second step. Transformations are accomplished via template matching. The basis for a template is a network with m gates that realizes the identity function. If a sequence in the network to be synthesized matches more than half of a template, then a transformation reducing the gate count can be applied. All templates for m ≤ 7 are described in this paper. are described in this paper.

52 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20236
202219
202151
202047
201938
201847