Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

Convolutional interleaving and de-interleaving circuit and method thereof

Abstract: A convolutional interleaving and de-interleaving circuit and the method thereof are provided. The convolutional interleaving and de-interleaving circuit includes an initial address generator, a first address generator, a second address generator, an address mixer, an adder, a controller and a memory. Wherein, the controller enables those address generators to provide or store corresponding channel addresses. Further, an adder is shared and memory addresses are appropriately arranged so as to reduce the requirement of registers. Accordingly, the required gate count and the chip layout area can be reduced.

Reed-Solomon multiplication method

Abstract: A method for computing Reed-Solomon error control checkbytes in reduced time and with reduced gate count. Two syndromes, s 0 and s 1 , are computed for a sequence of data elements, using a selected primitive a that satisfies a selected primitive polynomial relation p(α)=0. Each of two checkbytes, c 0 and c 1 , is expressed as a linear combination of the syndromes s 0 and s 1 , where each coefficient of each linear combination is expressed as a single power of the primitive α, which is stored at the checkbyte generator for multiple use. This approach reduces gate count and associated time delay in formation of the usual Reed-Solomon multiplier coefficients.

Hardware Implementation of HEVC CABAC Binary Arithmetic Encoder

Abstract: In this paper, hardware architecture of BAE (binary arithmetic encoder) was proposed for HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) encoder. It can encode each bin in a single cycle. It consists of controller, regular encoding engine, bypass encoding engine, and termination engine. The proposed BAE was designed in Verilog HDL, and it was implemented in 180 nm technology. Its operating speed, gate count, and power consumption are 180 MHz, 3,690 gates, and 2.88 mW, respectively.

Low Cost 1D DCT Core for Multiple Video Codec

Abstract: The expandability of high demands for multimedia applications brings out more and more video standards for improving the coding and compression efficiency. As the most commonly used transform, Discrete cosine transform (DCT) achieves excellent energy compaction property and good compression efficiency. Hardware sharing is the mostly used efficient strategy to reduce the cost for video codec. Based on traditional matrix factorization, this paper makes three observations to direct the design of proposed hardware sharing architecture. The proposed architecture can be generally used to compute 8×8 DCT of AVS, H.264, VC-1 and HEVC in a low cost way, and can be used to decode Full-HD and WQXGA formate video sequences in real time. The design has been synthesized in 0.13μm technology. The synthesis results show that the proposed architecture achieves 76.9% reduction in gate count, 85.6% decrease in power consumption and 35% improvement in operational speed in comparison with other existing designs.

A Comparative Analysis of Binary Decision Diagram Reordering Algorithms for Reversible Circuit Synthesis

Abstract: As billions of transistors are being placed on a few square millimeters of silicon, power dissipation is becoming a more crucial factor to be tackled for high performance computing. Reversible circuit synthesis has been considered as a promising direction for low power design due to its information lossless behavior. In addition, it forms the basis for quantum computing. However, synthesis of reversible circuits cannot be achieved with the classical approaches for irreversible logic due to the additional imposed constraints, consequently, neither fan-out nor feedback are allowed. Binary Decision Diagrams (BDDs) have been proposed as a compact data structure to represent a boolean function. They have been exploited to synthesize reversible circuits through proper mapping of each BDD’s node into a cascade of reversible Toffoli gates. Nevertheless, reordering of BDD’s nodes before circuit synthesis significantly impacts the overall cost of the synthesized circuit. In this paper, we present a comparative study for BDD reordering algorithms in terms of the cost of the generated reversible circuit. The studied algorithms include greedy, dynamic programming, and heuristic based approaches. The cost metric includes the number of lines, gate count, and quantum cost. Experimental results show that meta heuristic-based BDD reordering algorithms outperform other algorithms in terms of the overall synthesized circuit cost with slightly additional runtime. Thereafter, we conclude with a proposal for a new framework for reversible logic synthesis.