Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

A High Speed Deblocking Filter Architecture for H.264/AVC

Abstract: In this paper, a high speed deblocking filter architecture for H.264/AVC is proposed to process one macroblock in 48 clock cycles and give real-time support to QFHD (3840x2160) @60fps sequences at less than 100MHz. 4 edge filters organized in 2 groups for simultaneously processing vertical and horizontal edges are applied in this architecture to enhance its throughput. While parallelism increases, pipeline hazards arise owing to the latency of edge filters and data dependency of deblocking algorithm. To solve this problem, a zig-zag processing schedule is proposed to eliminate the pipeline bubbles. Data path of the architecture is then derived according to the processing schedule and optimized through data flow merging, so as to minimize the cost of logic and internal buffer. Meanwhile, the architecture"s data input rate is designed to be identical to its throughput, while the transmission order of input data can also match the zig-zag processing schedule. Therefore no intercommunication buffer is required between the deblocking filter and its previous component for speed matching or data reordering. As a result, only one 24x64 two-port SRAM as internal buffer is required in this design. When synthesized with SMIC 130nm process, the architecture costs a gate count of 30.2k, which is competitive considering its high performance.

Experimental evaluation of concurrent fault simulation algorithms on scalable, hierarchically defined test cases

Abstract: The authors have implemented three concurrent fault simulation algorithms and applied them to several circuit families. The algorithms are concurrent fault simulation (CFS), hierarchical concurrent fault simulation (HCFS), and a modification of HCFS called bundled hierarchical fault simulation (BHCFS). In BHCFS, a structure is imposed upon the simulation error lists, which can produce a significant reduction in simulation run time. A prototype of each algorithm has been applied to circuit families of varying size to generate actual run-time data. The circuits are scalable (to some granularity) in gate count. This property allows the simulator run-time data to be presented as a function of circuit size without the effects of varying circuit topology. It is shown experimentally that the run time for BHCFS grows nearly linearly with acyclic circuit gate count but approaches a higher order in tightly connected sequential circuits. It is also confirmed that HCFS exhibits near N log N behaviour in circuits which have reasonably well-balanced design hierarchy. In absolute run time, both hierarchical algorithms outperformed flat CFS at the gate level in all examples except one, which had an extremely unbalanced hierarchy. Overall, BHCFS shows the best performance in acyclic circuits and good performance in loosely coupled sequential circuits. >

UICE: a low-power high-speed cryptographic module for RFID and embedded systems

Abstract: Since Radio-Frequency Identification (RFID) systems have become commonplace in access control and security applications, the usage and importance of cryptographic co-processors in RFID transponder devices has grown significantly Improved vehicle security systems, also known as immobilizers, are required due to increased vehicle theft worldwide Such devices, and embedded systems in general, must provide high security at low cost and low power In order to overcome proprietary algorithms with respect to the system manufacturers, a new Universal Immobilizer Crypto Engine (UICE) is proposed This UICE algorithm is tailored to 8-bit microprocessor architectures and is therefore very fast in software and hardware The dedicated hardware implementation leads to a small gate count, because the registers for input (challenge) and output (response) are shared The important non-linear function, in this case an 8 /spl times/ 8 S-Box, may be built as a gate array or small ROM, which has the advantage of flexibility Several tests - statistical and random-number - have been performed in order to analyze the strength of the algorithm So far no weakness was found after ten rounds of encryption

High-Throughput LDPC Decoder for Long Code-Length

Abstract: We have designed and implemented the LDPC decoder with memory-reduction method to achieve high-throughput and practical hardware size for long code-length The decoder decodes (3,6)-11520-bit regular LDPC codes using modified min-sum algorithm The decoder achieves a throughput of 312 Mb/s at an operating frequency of 69 MHz with 20 iterative decoding The gate count is 2M gates

CRISP: coarse-grain reconfigurable image signal processor for digital still cameras

Abstract: This paper presents a novel preview-based coarse-grain reconfigurable image signal processor (CRISP) for digital still cameras (DSCs). The two modes in DSCs, which have quite different hardware considerations, make traditional implementation methods inefficient. One is preview mode, which needs realtime constraints and the other one is picture-taking mode, which requires high flexibility and capability for various algorithms in it. Low cost design of CRISP considers simpler image pipelines in preview mode and extends flexibility required in picture-taking mode with proper hardware resources devotion. Algorithmic similarity in image pipelines and successful hardware classification lead it to a combination of low cost and high efficiency. Coarse-grain modules connected by reconfigurable interconnection make it a good compromise between dedicated hardware and DSPs, which are suitable for only one, not all of two modes in DSCs respectively. The experimental results show that the total gate count of it is 38.6K with 5.8K byte memory. It can save more than 75% area from high end DSP, such as Trimedia TM1300. Besides, CRISP reduces execution cycle number of image pipeline tasks, such as 2-D filters to only 0.17% of that required by TM1300.