Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

Test Pattern Generator Design Optimization Based on Genetic Algorithm

Abstract: In this paper an approach for the generation of deterministic test pattern generator logic composed of D-type and T-type flip-flops is described. The approach employs a genetic algorithm to find an acceptable practical solution in a large space of possible implementations. In contrast to conventional approaches our genetic algorithm approach reduces the gate count of built-in self-test structure by concurrent optimization of multiple parameters that influence the final solution. Results of experiments with combinational benchmarks demonstrate the efficiency of the proposed evolutionary approach.

An efficient implementation of PRNGs based on the digital sawtooth map: Research Articles

Abstract: In this paper, the sawtooth map digitally implemented is analysed to evaluate its suitability for pseudo-random binary numbers generation. Period and statistical properties of the sequences generated by the digital map are evaluated versus arithmetic precision, approximation strategy and characteristic parameter of the map.In general, the digital implementation of the sawtooth map requires the use of a multiplier, which is quite expensive in terms of gate count. However, results show that values of design parameters that lead to adequate statistical features and to a relatively high period also allow for significantly reducing the complexity required in the implementation.To better evaluate performance of the digital sawtooth map as a pseudo-random number generator, it is compared to a linear feedback shift register with the same number of flip-flops, which is well known for its output sequences with a long period, appealing statistical quality, and for a reduced gate count. Performance comparison and implementation on a programmable logic device show that the digital sawtooth map is suitable for pseudo-random number generation, also requiring a relatively small amount of hardware. Copyright © 2004 John Wiley & Sons, Ltd.

Design of Parity Preserving Arithmetic and Logic Unit using Reversible Logic Gates

Abstract: Arithmetic and Logical Unit (ALU) is one of the key aspects of the digital world. In generally, it requires a colossal amount of power. This paper outlines a new design of one-bit Parity Preserving Reversible ALU circuit. To design the ALU with low power dissipation, we have used the concept of Reversible Logic computation. Conventional Circuits dissipate an enormous amount of power due to the loss of information bits in computation, but Reversible Circuits has no data loss as one on one mapping between outputs and inputs which leads to the minimization of power dissipation. In our design, we have used Parity Preserving Reversible Gates which are having Fault tolerance property as fault occurring at internal nodes results in an error at the output. So, Parity Preserving Reversible Gates is the one in which Output Parity remains same as of the Inputs. The aimed ALU has been carried out using Xilinx ISE 14.7 version software in Verilog HDL. To demonstrate the efficiency of proposed Parity Preserving Reversible Arithmetic and Logical Unit, each subpart is shown in terms of various parameters such as Quantum cost, Ancilla Inputs, Gate Count and Garbage Outputs and also a comparison with existing work is shown. The intended design is far better than the existing one because of its fault-tolerant capabilities. The proposed ALU extends its application over DNA mapping, Optical computation, cryptography, nanotechnology, quantum computing and digital signal processing.

Gate Count Comparison of Different 16-Bit Carry Select Adders

Abstract: Addition is the most fundamental computational process encountered in digital system. An area efficient carry select adder is proposed in this paper by comparing the Gate count of Regular and Modified 16-bit carry select adders with a proposed Common Boolean Logic carry select adder. In this paper, Gate count evaluation of Regular, Modified and proposed designs are given in terms of INVERTER, NAND and NOR Gates. The comparison results shows that the common Boolean logic carry select adder structure require lesser number of gates than that of Regular and Modified 16-bit carry select adder.