Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

Design and analysis of reversible multiplexer and demultiplexer using R-Gates

Abstract: The paper presents a reversible implementation of multiplexer and de-multiplexer, and evaluation of their quantum cost, gate count, garbage outputs and depth of the circuit. The simulation results are obtain edinXilinxISE version 14.1. Reversible logic circuits are designed and implemented using Verilog code. The circuit is beneficial for further designing of reversible digital designs with low power loss. The devices designed through this circuit are expected to have a better performance as compared to the existing circuits.

Area-delay-power efficient PSO based full adder in different technologies

Abstract: With the increasing complexity of electronic circuits and to meet the demand of high performance, the design and optimization of electronic circuits need to be automated with high degree of reliability and accuracy. In order to optimize hardware requirements of digital combinational circuits, evolutionary and innovative techniques need to be enforced at various levels such as at gate level and device level. One of the evolutionary technique Particle Swarm Optimization (PSO) algorithm motivated by the social behaviour of organism is used for the optimal design of combinational logic circuits with reduced gate count on MATLAB platform. PSO technique has been applied to optimize Full Adder circuit. Results are presented to support that the PSO based algorithm is better than Human Design Method in respect of time, labour and specially the gate count required to design digital combinational circuit. Later on that optimized circuit has been analysed by Microwind3.1 VLSI CAD Tool. Using the tool the parameters like Area, Power, Delay and Maximum and Average drain current are determined with 90nm, 65nm and 45nm technologies using BSIM4 Model. The results shown in this paper reflects that with technology scaling decreases the area, delay, power consumption and leakage current which are some of the major requirements of today's VLSI design.

DCT and CORDIC on a novel configurable hardware

Abstract: Discrete Cosine Transform (DCT) operations, used in compression algorithm, have great significance in image and signal processing applications where the cosine computation forms an integral part. The CORDIC (COrdinated Rotation Digital Computer) algorithm provides a simplistic and accurate platform to compute various trigonometric, linear and non-linear functions using only shift-add operations. Due to inherently repetitive nature of DCT and CORDIC function, it yields to efficient hardware implementations. This paper presents the implementation of DCT and CORDIC on a novel configurable architecture ported onto a state of the art FPGA. The proposed architecture uses only shifts and adds to perform multiplication, thereby reducing the gate count. The design takes 192 clock cycles and 336 clock cycles/image block to compute cosine using CORDIC and DCT, respectively. The L2 norm of the hardware reconstructed image is 15.77 at 84.37% compression on a 128×128 image and computes cosine (CORDIC) with accuracy upto 98%.

FPGA-based Stepper Motor Controller Design

Abstract: With the development of microelectronics technology,so that a chip can be integrated in the large system is possible In addition a larger gate count of the programmable logic device appeared to achieve such a system provides a very convenient and economical way This article describes the introduction of stepper motors,stepper motor according to work characteristics,using VHDL language on the controller design Achieved a two-axis stepper motor constant speed control mode,the parameter adjustment method is simple,in one or several chips on the CNC system to prepare for a larger structure