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Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.


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TL;DR: This paper connects the problem of upper bound of the gate count with the multiplicative complexity analysis of classical Boolean functions and explores the possibility of relaxing the ancilla and if that approach makes the upper bound tighter.
Abstract: Reversible computation is gaining increasing relevance in the context of several post-CMOS technologies, the most prominent of those being Quantum computing. One of the key theoretical problem pertaining to reversible logic synthesis is the upper bound of the gate count. Compared to the known bounds, the results obtained by optimal synthesis methods are significantly less. In this paper, we connect this problem with the multiplicative complexity analysis of classical Boolean functions. We explore the possibility of relaxing the ancilla and if that approach makes the upper bound tighter. Our results are negative. The ancilla-free synthesis methods by using transformations and by starting from an Exclusive Sum-of-Product (ESOP) formulation remain, theoretically, the synthesis methods for achieving least gate count for the cases where the number of variables $n$ is $< 8$ and otherwise, respectively.

2 citations

Journal ArticleDOI
TL;DR: The different parameters such as gate count,bage output and constant input are more optimized in the proposed fixed bit binary to binary coded decimal converter than the existing design.
Abstract: Reversible logic gates under ideal conditions produce zero power dissipation. This factor highlights the usage of these gates in optical computing, low power CMOS design, quantum optics and quantum computing. The growth of decimal arithmetic in various applications as stressed the need to propose the study on reversible binary to BCD converter which plays a greater role in decimal multiplication for providing faster results. The different parameters such as gate count,garbage output and constant input are more optimized in the proposed fixed bit binary to binary coded decimal converter than the existing design.

2 citations

Proceedings ArticleDOI
01 Dec 2018
TL;DR: The processor with encryption /decryption of 194 bit key and data is implemented selecting low cost optimized Xilinx Spartan 3E XC3S500/ FG320 and Speed Grade of -5 with the IDE toolXilinx ISE 9.2i.
Abstract: Resource constraint Wireless Sensor Networks requires the fast multipliers that are crucial for data processing. Scalar or Point multiplication, the most important operation of Elliptic Curve Cryptography (ECC) is carried out with Montgomery Multiplication which is implemented using Vedic and Encoded Multipliers. Both the multipliers are designed for basic finite field multiplication operations at lower levels of design that increases the overall performance of the cryptosystem in terms of speed, area, operating frequency and consumption of power. The encoded architecture has low gate count and it decreases the number of partial products in its multiplier architecture. In point doubling and point addition the multiplications are done by Encoded Multiplier and squaring using Urdhva Triyambhagyam Vedic Multiplier. For experimental purpose the crypto system is first implemented with GF (2$^{8}$) and expanded to GF (2$^{194}$). The synthesis result gives that delay of 3.510 nanoseconds for 8 bit point multiplication and 2608 nanoseconds for 194 bit. Upon device utilization it is 432 LUTs for 8 bit and 7455 for 194 bit architecture. The static power utilization for 194 bit is 178.43 mW. The processor with encryption /decryption of 194 bit key and data is implemented selecting low cost optimized Xilinx Spartan 3E XC3S500/ FG320 and Speed Grade of -5 with the IDE tool Xilinx ISE 9.2i. Hardware implementation is performed for GF (2$^{8}$) on Spartan 3E with input and output pins availability.

2 citations

Proceedings ArticleDOI
29 Nov 2001
TL;DR: The prototyping of a 32-bit Java embedded multimedia processor (MmP) by a 20k-gate FPGA with an enough instruction set is significantly faster than other Java-embedded processors by similar speed grade FPGAs.
Abstract: Still further improvement of multimedia processors is strongly expected to exploit more profitable features because they are essential for the ever-growing Internet. Those processors embedded with a user-friendly programming language Java as a common base are sophisticated mixed systems merging hardware and software. In order to reduce cost and effort in their designing, Field Programmable Gate Array (FPGA) prototyping is really an attractive approach. We describe here the prototyping of a 32-bit Java embedded multimedia processor (MmP) by a 20k-gate FPGA. The main scope with respect to our FPGA prototyping is the compatibility of space and clock speed. The switching speed of the FPGA is not so high grade due to its inevitable tradeoffs against gate count, which we cannot but keep in some degree to cover inherent Java features. Nevertheless, MmP works at the rate of more than 25 MHz owing to our totally minute adjustment through the developing process from hardware description to chip implementation. MmP with an enough instruction set is significantly faster than other Java-embedded processors by similar speed grade FPGAs. Our approach described here naturally abstracts maximum benefit even in case of other type ASIC and custom designs.

2 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20236
202219
202151
202047
201938
201847