Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

Flexible IME instruction and its architecture for various fast ME algorithms

Abstract: This paper proposes Integer-pel Motion Estimation (IME) specific instructions and their hardware architecture for Motion Estimation Specific Instruction-set Processor (MESIP). With pattern information using the pixel distance, the proposed IME instruction efficiently supports fast search algorithms. The proposed MESIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The gate count is about 25.5K gates for each Processing Element Group (PEG) which has 128 SAD PEs. The total hardware size is about 453K gates and the operating frequency is 188MHz for 1080p@30frames in real time. MESIP can reduce the hardware size about 26% and the number of operation cycles about 18% compared with the prior version of MESIP and comparable to the existing ASICs.

Universal Asynchronous Receiver / Transmitter (UART) Design for Hand Held Mobile Devices

Abstract: A Universal Asynchronous Receiver / Transmitter (UART) is responsible for performing the main task in serial communications with computers.Advanced Peripheral Bus (APB) is an interface defines in the advanced Microcontroller Bus Architecture (AMBA), which was introduced by ARM ltd and widely used as on-chip bus in system on-chip (Soc) designs. After coding the design, students will be required to develop verification plan describing verification strategy for the design.This is followed by verification environment development and simulation of design. Once design is cleared through functional verification students will develop synthesis strategy document. Afterwards synthesis scripts will be coded and design will be synthesizes on 45nm technology and timing checks will be performed. Synthesis report with final working frequency, gate count and chip area will be published.Project is targeted towards very low power handheld devices with operating voltage of 0.7-0.9V. Low power clock gating strategies will be developed and applied.Target operating frequency is 100 MHz and silicon area under 0.01 sq mm. Differentoptimization experiments will be conducted to ascertain best area to frequency trade off.Students will gain experience in developing architecture from given specification.Students will be exposed to developing micro architecture and describing it in VerilogHDL

RF/analog/digital SOI technology for GPS receivers and other systems on a chip

Abstract: Increasing numbers of military and aerospace systems require miniaturization and low power which can only be achieved by employing mixed mode combinations of RF, analog and digital circuits on the same chip. GPS receivers are an excellent example of the subsystem required to fit in small munitions or the soldier watch. At the same time, the requirements for jamming and spoofing resistance and encryption decoding increase the gate count to 20-30 Mgates. Similar in complexity the analog section may require 16-bit analog to digital converter for digital beam forming. Demanding RF front-end performance section includes the low noise amplifiers with noise figure below 2 dB and with associated gain of 30-40 dB. Such extreme mixed mode requirements can be only met with specialized technology like Silicon-on-Insulator (SOI) on high resistivity substrate. Such substrate provides excellent isolation and 10 dB lower noise than in bulk CMOS.

A 16-laser array for an optically reconfigurable gate array

Abstract: Demand is increasing daily for a robust VLSI chip that is useful for operating under a radiation-rich space environment, such as spacecraft, space satellites, and space stations. Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. The ORGA architecture is extremely robust for many failure modes caused by high-energy charged particles. This paper presents a robust 16-laser array for an optically reconfigurable gate array and its demonstration results.

Minimum gate delay edge counter

Abstract: An edge counter counting both rising and falling edges of an input signal is implemented with combinational logic, without using flip-flops. The combinational logic is designed using intermediate signals and state transitions producing an output signal having a cycle corresponding to a predetermined odd or even number of input signal edges, with the logic optimized and protected against entry into “stuck” states. A low power, low gate count edge counter is thus implemented with an output signal duty cycle at least as balanced as the input counter duty cycle.