Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

Novel IME instructions and their hardware architecture for ME ASIP

Abstract: This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs such as H.264/AVC and MPEG4. With the proposed specific instructions and hardware accelerators, it can handle the processing requirement of High Definition (HD) video. With parallel SAD Processing Elements (PEs) using pattern information, the proposed IME instruction supports not only the full search algorithm but also other fast search algorithms. The gate count is 77K gates for each Processing Element Group (PEG) which has 256 SAD PEs. The proposed ASIP with sixteen PEGs runs at 160MHz and can handle 1080p@30 frame in realtime.

A zero-overhead dynamic optically reconfigurable gate array

Abstract: This paper presents a zero-overhead dynamic optically reconfigurable gate array (DORGA) that uses the load capacitance of gates to construct a gate array to maintain its state during optical reconfiguration, and uses junction capacitance of photodiodes as configuration memory. It improves a reconfiguration overhead problem of the previously proposed DORGA. The reconfiguration procedure is executable without the overhead of optical reconfiguration by reducing the dispersion delay between optical reconfiguration circuits. This paper presents the design of 1,632 gate count zero-overhead DORGAs reduced the dispersion delay using a standard 0.35 /spl mu/m three-metal CMOS process technology.

FPGA Implementation of Pipeline Digit-Slicing Multiplier-Less Radix 22 DIF SDF Butterfly for Fast Fourier Transform Structure

Abstract: The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This paper presents FPGA implementation of pipeline digit-slicing multiplier-less radix 22 DIF (Decimation In Frequency) SDF (single path delay feedback) butterfly for FFT structure. The approach taken; in order to reduce computation complexity in butterfly multiplier, digit-slicing multiplier-less technique was utilized in the critical path of pipeline Radix-22 DIF SDF FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The multiplier input data was sliced into four blocks each one with four bits to process at the same time in parallel. The new architecture was investigated and simulated with MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board. Consequently, the Virtex-II FG456 Proto board was used to implement and test the design on the real hardware. As a result, from the findings, the synthesis report indicates the maximum clock frequency of 555.75 MHz with the total equivalent gate count of 32,146 is a marked and significant improvement over Radix 22 DIF SDF FFT butterfly. In comparison with the conventional butterfly architecture design which can only run at a maximum clock frequency of 200.102 MHz and the conventional multiplier can only run at a maximum clock frequency of 221.140 MHz, the proposed system exhibits better results. It can be concluded that on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure is an enabler in solving problems that affect communications capability in FFT and possesses huge potentials for future related works and research areas.

Performance trade-off in decision diagram based synthesis of reversible logic circuits

Abstract: Reversible computing is an emerging and promising technique due to its wide applications in quantum, optical and DNA computing and many more. Reversible circuit synthesis is a main focus for researchers as conventional synthesis techniques are not suitable for reversible circuits. Our work focuses on BDD based synthesis as it has capabilities of realizing circuit for large boolean functions unlike other reversible synthesis methods. Existing BDD based synthesis techniques rely on positive [1] and negative [2] controlled Toffoli gates. In this paper work we explore BDD based synthesis technique along with evolutionary computation method. We employed Fredkin and elementary CNOT gate library. Experimental results demonstrate that this approach reduces the gate count and quantum cost at the cost of increase in the number of lines.