Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

High-Level Design Methodology Overview

Abstract: Major advances in fabrication technology have made possible high-integration, large gate count ASICs. Hardware description languages and logic synthesis have had a significant impact on the design process of these ASICs. With the adoption of HDL-based design, there has emerged a high-level design flow based on synthesis.

Pulsed Decimal Encoding for IoT Single-Channel Dynamic Signaling

Abstract: Pulsed-Index Communication (PIC) is a recent technique for single-channel communication that is based on the principle of transmitting the indices of only the ON bits as a series of pulse streams. In this paper, a modified version of PIC, called Pulsed Decimal Communication (PDC), is presented that uses the same underlying principle but with key improvements in data rate and reliability. Like PIC, PDC is a protocol for single-channel, high-data rate, low-power dynamic signaling that does not require any clock and data recovery. It consists of a three-step algorithm, comprising a segmentation, an encoding, and a sub-segmentation step to achieve higher data rates. The segmentation step splits the data word into smaller segments and therefore smaller decimal numbers to represent them. The encoding step reduces the number of ON bits in the data and relocates them to lower indices. The sub-segmentation step further splits the segments into smaller sub-segments. The complete process significantly reduces the total number of pulses required for transmitting binary data, thus improving the data rate by about 78%. A theoretical model of the PDC protocol is exploited to estimate its data rate and derive the optimum segmentation. Furthermore, PDC is shown to be more reliable than PIC as it eliminates the variations in the number of symbols to be transmitted. The FPGA and ASIC (65 nm technology) implementations of PDC show that the low-power operation and small footprint of PIC are preserved. PDC consumes around \(25\,\upmu \mathrm{W}\) of power at a clock frequency of 25 MHz with a gate count of approximately 2150 gates.

An Efficient Hardware Design for Euclidean Key Equation Solver in Reed-Solomon Decoders

Abstract: Reed-Solomon codes have been widely used in many communication applications such as satellite communications, fixed broadband wireless access, etc. After obtaining the syndrome polynomial, there are approaches to solve the key equation for error locations and error magnitude. Two most well known approaches are the Euclidean and Berlekamp-Massey (BM) algorithms. This paper presents an efficient hardware implementation for the Euclid's algorithm. According to the design results, the proposed low latency design has only about 72.5% clock cycles of those in H. Lee (2003) and Hsie-Chia Chang and Chen-Yi Lee (2001). In addition, the chip synthesis report shows the proposed design has only 63.6% gate count of H. Lee (2003) and 27% gates of Hsie-Chia Chang and Chen-Yi Lee (2001), respectively. The new design is also compared to the BM algorithm and exhibits shorter latency in several erasure cases

A high performance 2-dimensional VLSI architecture for H.264/AVC Variable Block Size integer motion estimation

Abstract: Variable Block Size (VBS) motion estimation has been adopted by H.264/AVC for its compression efficiency and high video quality. In this paper we propose parallel 2-D architecture for computing the Motion Vectors (MV). This 2-D systolic array architecture is composed of 16 Processing Element (PE) with Carry Save Adder (CSA) compressor and comparators to compute Sum of Absolute Differences (SAD) of 4×4 macro block. By data reuse scheme using raster scan method the Sum of Absolute Difference (SAD) for variable blocks 8×4, 4×8, 8×8, 16×8, 8×16, 16×16 are computed from the SAD of 4×4 sub blocks resulting in 41 SADs. With the reduced computational complexity for the search range [16×16] our design operates at the frequency of 689.65MHz with the throughput of 43.1Mega blocks per second and the power dissipation is 246.13μW. Our design is synthesized by using Cadence RTL Compiler using TSMC 45nm CMOS technology with a gate count of 21.742k gates.

Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder

Abstract: Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, a simplified basic-set trellis min-max (sBS-TMM) algorithm that is especially efficient for high-order Galois Fields, is proposed for the variable node processing to reduce the complexity of the variable node unit (VNU) as well as the whole decoder. The decoder architecture corresponding to the proposed algorithm is designed for the (837, 726) NB-LDPC code over GF(32). The implementation results using 90-nm CMOS technology show that the proposed decoder architecture reduces the gate count by 21.35% and 9.4% with almost similar error-correcting performance, compared to the up-to-date works.