Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

Synthesis of Reversible Logic Using Enhanced Genetic Programming Approach

Abstract: A new enhanced reversible logic circuit synthesis method was developed using reversible gates that include NOT, CNOT (Feynman), Toffoli, Fredkin, Swap, and Peres gates. The synthesis method was done using newly developed genetic programming. Usually previous synthesis methods that uses genetic algorithms or other similar evolutionary algorithms suffers a problem known as blotting which is a sudden uncontrolled growth of an individual (circuit), which may render the synthesis inefficient because of memory utilization, making the algorithm difficult to continue running and eventually stack in a local minima, there for an optimized reversible circuit may not be generated. In this method the algorithm used was blot free, the blotting was carefully controlled by fixing a suitable length and size of the individuals in the population. Following this approach, the cost of generating circuits was greatly reduced giving the algorithm to reach the end of the last designated generation to give out optimal or near optimal results. The results of the circuits generated using this method were compared with some of the results already in the literature, and in many cases, our results appeared to be better in terms of gate count and quantum cost metrics.

Nanotechnology-Based Efficient Fault Tolerant Decoder in Reversible Logic

Abstract: Reversible logic has received great attention in last few years as it dissipates very low power. This paper presents the reversible logic synthesis for the n-to-2n fault tolerant decoder, where n is the number of data bits. A low cost 6 × 6 reversible gate is proposed to design a 2-to-4 reversible fault tolerant decoder which has least delay. An algorithm is derived to construct higher bit order decoder. Theoretical explanations certify the novelty of the proposed design. Comparing with previous works, the proposed design shows significant reduction in gate count, quantum cost and delay, which are 66.66%, 8.33%, 16.66%, respectively, with respect to the corresponding metrics of the best existing 2-to-4 fault tolerant decoder. Area and power consumption of the proposed circuit are also estimated.

A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35/spl mu/m CMOS technology

Abstract: This paper presented the design of the largest 476-gate count DORGA fabricated by using 0.35 /spl mu/m three-metal CMOS technology. In the case of reconfiguring DORGA at 100MHz, the required optical power was estimated 2.24 W. At that time, the reconfiguration data transfer rate of the DORGA VLSI chip reaches 369.6 Gbit/s.

Design of 128x8 Pixel Array Fingerprint Sensor with a CapacitiveSensing Circuit Technique for Image Enhancement

Abstract: This paper proposes 128x8 array swipe type fingerprint sensor with a capacitive-sensing technique for image enhancement. The circuit of one pixel includes a pixel level chargesharing and charge pump to replace an ADC. The circuit also adopts the circuit technique that improves quality of dry finger image captured with capacitive fingerprint sensor LSIs. The proper operation is validated by HSPICE for one-pixel and RTL simulation including logic synthesis for a full chip design on condition of 0.35μm typical CMOS process and 3.3V power. The layout is performed by full custom flow for one-pixel and auto P&R for a full chip. The area of a full chip is 0.161mm 2 (9013μm x 1781μm) and the gate count is 303,329. The area of one-pixel is 58 x 58 μm 2 . Pitch is 60 μm and image resolution is 423dpi.

Testing in nanometer technologies

Abstract: Summary form only given. The last 25 years has seen a dramatic increase in gate count and the Design for Testability techniques such as Full Scan, LSSD, BIST, etc. have been developed to cope with this. However, there is now a significant difference brought on by the technology developments facing us. The onset of deep sub-micron (now currently alluded to as Nanometer Technology) is changing the way chips are being designed and manufactured. Because of the large capacity of these new chips, plus the expense of new designs, embedded systems are setting the pace for today and the future. New problems are arising that are driving design automation to integrate all the tools that are needed to successfully take a design from concept to reality in this new design environment. Test is one part of this process that is getting significant attention. An area once classified as a "back end" process in the design flow is moving closer to the "front end". Design methodologies are incorporating test-related structures in the beginning of the design cycle. In addition, standards to manage the test complexity of these large designs are being proposed. For example, IEEE P1500 is working towards defining a structure for embedded cores such that tests can be delivered to these cores. This alone is a strong challenge for the Test Community. It is clear that the design and testing of embedded systems is the key challenge facing the Test Community.