Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

Low-energy configurable syndrome/chien search multi-channel Reed Solomon decoder

Abstract: This paper presents a low-energy configurable syndrome/chien search pipelined Reed-Solomon RS (255; 239) decoder architecture using Euclidean algorithm. The configurable structure enables the syndrome and Chien search blocks to work either in serial mode which needs 255 clock cycle to finish, or in two parallel mode which needs 128 clock cycle to finish. The Euclidean algorithm block can be shared with 8 or 16 channels based on the required rate per channel. In serial mode, the configurable cells enable the Euclidean algorithm block to be shared between 16 channels each channel takes rate up to 4 Gbps. In two parallel mode, the configurable cells enable the Euclidean algorithm block to be shared between 8 channels each channel takes rate up to 8 Gbps with latency reduction of 47% and power reduction of 27% relative to using two serial channels in parallel. The 16 channel RS (255; 239) decoder has been implemented by 0.13µm CMOS IBM standard cells with a gate count of 200K and area of 20mm2, simulation results show this approach can work successfully at the data rate 64Gbps

Implementation of Low-Power High-Performance VLSI Architecture for High Throughput Considerations based on CAVLC Decoding

Abstract: This paper proposes a novel algorithm and its very large scale integration design for context-based adaptive variable length code (CAVLC) decoding. In order to improve throughput of CAVLC decoder, we propose two new methods, which are multiple level decoding (MLD) and nonzero skipping for run−before decoding (NZS). By performing parallel operations on the level decoder, MLD can decode two levels in one cycle at most situations, and NZS can produce several values of run−before in the same cycle. These two methods have the advantages of low complexity and regularity. The proposed architecture needs 141 cycles/macroblock. Moreover, the proposed CAVLC decoder can run at 33.5MHz to meet the real time requirement for 1920×1088 resolution. The power consumption for the 1920×1088 resolution is about 1.83mW. The operation frequency can be reduced about 29.1% to 71.5% compared with other architectures. With an aid on a lower operation frequency, it is suitable for many low power applications. The synthesis result shows that the gate count is 13 175 gates, and the maximum frequency can archive 160 MHz.

Quantum Gate Pattern Recognition and Circuit Optimization for Scientific Applications

Abstract: There is no unique way to encode a quantum algorithm into a quantum circuit. With limited qubit counts, connectivities, and coherence times, circuit optimization is essential to make the best use of near-term quantum devices. We introduce two separate ideas for circuit optimization and combine them in a multi-tiered quantum circuit optimization protocol called AQCEL. The first ingredient is a technique to recognize repeated patterns of quantum gates, opening up the possibility of future hardware co-optimization. The second ingredient is an approach to reduce circuit complexity by identifying zero- or low-amplitude computational basis states and redundant gates. As a demonstration, AQCEL is deployed on an iterative and efficient quantum algorithm designed to model final state radiation in high energy physics. For this algorithm, our optimization scheme brings a significant reduction in the gate count without losing any accuracy compared to the original circuit. Additionally, we have investigated whether this can be demonstrated on a quantum computer using polynomial resources. Our technique is generic and can be useful for a wide variety of quantum algorithms.

Design of Area Optimized Arithmetic and Logical Unit for Microcontroller

Abstract: Arithmetic and Logic Unit (ALU) can be understood with basic knowledge of digital electronics. The advantage of knowing ALU in detail is two-folded: firstly, programming of the processing device can be efficient and secondly, can design a new ALU architecture as per the various constraints of the use cases. The miniaturization of digital circuits can be achieved by either reducing the size of transistor (Moore’s law) or by optimizing the gate count of the circuit. The first has been explored extensively while the latter has been ignored which deals with the application of Boolean rules and requires sound knowledge of logic design. The ultimate outcome is to have an area optimized architecture/approach that optimizes the circuit at gate level. Here in this work, we have attempted to design an ALU which is area efficient while being loaded with additional functionality necessary for microcontrollers. One novel approach in our work is that the concept of hard-wired architecture (for multiplier and divider) is borrowed from Digital Signal Processors. Another aspect worth mentioning is the implementation of barrel shifter which will considerably reduce the execution time during the execution of shift/ rotate operations. The structural modeling is used in the design of the ALU which contributes to the reduction in the usage of number of LUTs and slices. The hardware design is made via Xilinx 9.1 ISE and verified using ModelSim. The results are very encouraging, and it seems that a thorough understanding and proper implementation of ALU will allow us to put other units in their place.

An Evaluation of Design Framework for Min-Sum Irregular LDPC Decoders

Abstract: Design of LDPC decoder depends on its check matrix. Since there exist a lot of check matrices with various sizes, it is not feasible to design a dedicated LDPC decoder for each check matrix. This work aims to make a versatile design framework to generate an LDPC decoder for each given check matrix. We consider a method to reduce the circuit area, focusing on the feature of the check matrix of 5G. In this paper, we present evaluation results of our framework, including gate count evaluations. We evaluated circuit areas of the decoders conforming to 5G. In the case of a check matrix where the number of information bits is about 120, the number of gates is about 3.7 M gates.