Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

Reversible Gate Mapping into QCA Explicit Cells Packed with Single Layer

Abstract: MOS based circuits and computing devices are facing challenge related to energy dissipation, short channel effect and device density. The state of the art technology is driven towards Quantum cellular automata (QCA) computing with an emphasis on a high-speed and smaller area. QCA is a new computing technology that is made of quantum cell restraining two electrons and two dots. In this paper, a novel design of Fredkin, Toffoli, and Feynman gate layout is designed using the molecular QCA concept. Presented cell layout of newly circuit validity is verified by QCADesigner software. Further, a large number of articles are reviewed and comparison results are presented to show the optimal results such as cell count, majority gate count, bounded box area, and clock utilize. In this work, QCA and reversible logic combined together and the proposed designs have less bounded box area and delay, which is an essential part of the next-generation computing.

A Low Power Design of H.264 Codec Based on Hardware and Software Co-design

Abstract: In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-Core Platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720×480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400㎒@30fps with CIF(Common Intermediated Format) and about 100k per core for H.264 decoder.

Smart Arbitration System for Multiprocessor AMBA Interface in System on Chip

Abstract: This paper describes the efficient arbitration scheme of an interface that provides access by multiple AMBA processors to targets in SoC (System on the Chip). The arbiter receives requests from several processors and issues grant signals by using its internal arbitration process to that processor allowed to get control over the bus through the AHB interface. The interface is common for all the accessing processors to decide who’s address, control signals, read data and write data to access any specific targets out of many like RAM or registers or others. The HDL modelling was done using Verilog HDL, a simulation by Cadence and Modelsim Simulator, and hardware implementation using Xilinx Pegasus FPGA device. FPGA device is used for quick implementation at its site without going foundry so that its hardware impact can be sorted out. It can be implemented in ASIC (Application Specific Integrated Circuit) too, for low gate count, higher speed low power for any SoC. The processor interface is the significant and critical block determining the controlling mechanism to provide processor access inside slave targets inside any system. A single processor was used previously. But modern systems are very sophisticated in respect of speed, complexity and size. To op the need for a complex system, multiple processors are put in Chip and the arbitration system’s job is to figure out efficient access by several processors. This research addresses efficient multiprocessor access by implementing a smart arbitration mechanism to provide grants to the processors. AMBA bus protocol is the industry-standard protocol and very convenient to use with any off the shelf macro available for the high tech industry.

A Full HD High Profile H.264/AVC Hardware Encoder with Frame Memory Access Minimizing ME Architecture

Abstract: We present a full HD H.264/AVC High Profile hardware encoder based on fast motion estimation (ME). Most processing cycles are occupied with ME and use external frame memory (SDRAM) access to fetch samples, which degrades the performance of the encoder. An approach to pixel subsampling fast ME which uses shared memory can solve these problems. The proposed algorithm achieves an 87.5% reduction of computational complexity compared with the full search algorithm in the JM reference software. It is feasible to perform the algorithm at a 270 ㎒ clock speed for 30 frame/s real-time full HD hardware encoding. Its total gate count is 872k, and internal SRAM size is 41.8 kB.

A Reliable implementation of Security-Enabled Architecture with area optimized symmetric Cryptography

Abstract: My project specifies a symmetric Cryptography technique which provides same keys to Cipher and Decipher to transfer the information for reducing the design complexity and AES (Advanced Encryption Standard) which provokes high security. The transferred information was stored securely in the memory unit. By implementing this design, the results can be accomplished that the optimized area is required to integrate the chip with the gate count of 22618, here shown that gate elements are reduced up to 53.98% in comparison with earlier methods and also providing the similar security as well as reduced power consumption of 43.907mw.