Topic
Gate count
About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.
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TL;DR: This paper presents a high performance design for Context-Based Adaptive Variable Length Coding (CAVLC), used in the H.264/AVC standard, with a two-stage encoder to make the scan and encode stage work simultaneously.
Abstract: This paper presents a high performance design for Context-Based Adaptive Variable Length Coding (CAVLC) used in the H.264/AVC standard. A two-stage encoder is proposed to make the scan and encode stage work simultaneously. The scan engine scans four coefficients at each cycle. Parallel encoder for four “levels” and parallel encoder for four “Run_before” are adopted to accelerate the encode engine. Only 120 cycles at most are needed to process one MB. The proposed CAVLC encoder can support 4Kx2K@60fps (frame per second) real-time encoding at 250MHz and the gate count is about 32k.
01 Jan 2014
TL;DR: Modified booth algorithm and reversible logic functions for radix-8 are described, less delay is produced compared to normal multiplication process and the number of partial products is reduced which will reduce maximum delay count at the output.
Abstract: — This paper describes the concept of multiplication by using modified booth algorithm and reversible logic functions for radix-8. By using Modified booth algorithm, less delay is produced compared to normal multiplication process. This booth algorithm also reduces the number of partial products which will reduce maximum delay count at the output. Reversible logic has the advantage of reducing the gate count, garbage outputs as well as constant inputs. Results are compared with Radix-2 and Radix-4 Booth multiplier. This modified booth algorithm is synthesized and simulated by using Xilinx 8.1 ISE simulator and ModelSim.
22 May 1998
TL;DR: In this paper, free-space optical interconnections within a single chip can slow of halt the growth in the number of metal levels required as gate count increases, and the benefits of these benefits leads to interesting conclusions and questions.
Abstract: Free-space optical interconnections within a single chip can slow of halt the growth in the number of metal levels required as gate count increases. Quantifying these benefits leads to interesting conclusions and questions.
25 Jul 2012
TL;DR: In this paper, the authors present a detection and compensation method of alignment errors between a programmable ORGA and a writer system to alleviate the shortcoming of conventional ORGAs, where the alignment errors arise when the ORGA is recorded with a writer.
Abstract: Recently, optically reconfigurable gate arrays (ORGAs) consisting of a gate array VLSI, a holographic memory, and a laser array have been developed to achieve a huge virtual gate count that is much larger than those of currently available VLSls. Consequently, ORGAs with more than tera-gate capacity will be realized by exploiting the storage capacity of a holographic memory. However, in contrast to current field-programmable gate arrays (FPGAs), conventional ORGAs have an important shortcoming: alignment errors arise when a programmable ORGA is recorded with a writer system. When programming a programmable ORGA along with alignment errors between the programmable ORGA and its writer system, the reconfiguration speed of the programmable ORGA is decreased. This paper therefore presents a detection and compensation method of alignment errors between a programmable ORGA and a writer system to alleviate that shortcoming.
01 Jan 2009
TL;DR: 2 stage pipeline 64b/66b Encoder/Decoder which operates at 156.25MHz standard specification and designed to minimize clock latency as possible as much as possible to implement PCS of 10GBASE-R type.
Abstract: In this paper, to implement PCS (Physical Coding Sublayer) of 10GBASE-R type, we present 2 stage pipeline 64b/66b Encoder/Decoder which operates at 156.25MHz standard specification and designed to minimize clock latency as possible as we can. The proposed circuit was designed based on Verilog hardware description language and measured for functional verification on VertexII-1000fg456 chip of Xilinx Inc.. Total equivalent gate count is 47,303 and estimated power consumption is 351mW at Vcc 3.3V.