Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

A Low-Latency Low-Power QR-Decomposition ASIC Implementation in 0.13 $\mu{\rm m}$ CMOS

Abstract: This paper presents a hybrid QR decomposition (QRD) design that reduces the number of computations and increases their execution parallelism by using a unique combination of Multi-dimensional Givens rotations, Householder transformations and conventional 2-D Givens rotations. A semi-pipelined semi-iterative architecture is presented for the QRD core, that uses innovative design ideas to develop 2-D, Householder 3-D and 4-D/2-D configurable CORDIC processors, such that they can perform the maximum possible number of vectoring and rotation operations within the given number of cycles, while minimizing gate count and maximizing the resource utilization. Test results for the 0.3 mm2 QRD chip, fabricated in 0.13 μm 1P8M CMOS technology, demonstrate that the proposed design for 4×4 complex matrices attains the lowest reported processing latency of 40 clock cycles (144 ns) at 278 MHz and dissipates 48.2 mW at 1.3 V supply and 25°C. It outperforms all of the previously published QRD designs by offering the highest QR processing efficiency.

Reducing the Gate Count of Bitslice DES.

Abstract: This paper describes various techniques to reduce the number of logic gates needed to implement the DES S-boxes in bitslice software. Using standard logic gates, an average of 56 gates per S-box was achieved, while an average of 51 was produced when non-standard gates were utilized. This is an improvement over the previous best result, which used an average of 61 non-standard gates.

Efficient and flexible gps receiver baseband architecture

Abstract: The present invention provides a new baseband integrated circuit (IC) architecture for direct sequence spread spectrum (DSSS) communication receivers. The baseband IC has a single set of baseband correlators serving all channels in succession. No complex parallel channel hardware is required. A single on-chip code Numerically Controlled Oscillator (NCO) drives a pseudorandom number (PN) sequence generator, generates all code sampling frequencies, and is capable of self-correct through feedback from an off-chip processor. A carrier NCO generates corrected local frequencies. These on-chip NCOs generate all the necessary clocks. This architecture advantageously reduces the total hardware necessary for the receiver and the baseband IC thus can be realized with a minimal number of gate count. The invention can accommodate any number of channels in a navigational system such as the Global Positioning System (GPS), GLONASS, WAAS, LAAS, etc. The number of channels can be increased by increasing the circuit clock speed.

An Efficient FFT Engine With Reduced Addressing Logic

Abstract: In this study, an improved butterfly structure and an address generation method for fast Fourier transform (FFT) are presented. The proposed method uses reduced logic to generate the addresses, avoiding the parity check and barrel shifters commonly used in FFT implementations. A general methodology for radix-2 N-point transforms is derived and the signal flow graph for a 16-point FFT is presented. Furthermore, as a case study, a 16-point FFT with 32-bit complex numbers is synthesized using a CMOS 0.18 mum technology. The circuit gate count analysis indicates that significant logic reduction can be achieved with improved throughput compared to the conventional implementations.

A low complexity complex QR factorization design for signal detection in MIMO OFDM systems

Abstract: Complex QR factorization is a fundamental operation used in various MIMO signal detection algorithms. In this paper, we revise the Givens Rotation based factorization algorithm and develop an efficient scheme working in the real number domain. The complex matrix is first extended into a block-wise symmetric real number counterpart. The proposed scheme can reduce the computing complexity to almost one half by exploiting the symmetric property. Computing complexity analysis also shows the superiority of our scheme over various factorization schemes. Finally, subject to the EWC 802.11n recommendation, a novel systolic array design featuring fully parallel and deeply pipelined processing was presented. CORDIC algorithm is employed to implement the required rotation operations with low circuit complexity. Synthesis results in TSMC 0.18mum process indicate the proposed design, with a gate count of merely 17.06 K and a maximum clock rate of 202 MHz, can admit a new 2 x 2 complex matrix for factorization in every 8 clock cycles.