Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

A 16-configuration-context dynamic optically reconfigurable gate array with a dependable laser array

Abstract: Demand is increasing daily for a large-gate-count robust VLSI chip that is useful in a radiation-rich space environment. Optically reconfigurable gate arrays (ORGAs) have been developed to realize a much larger virtual gate count than those of current VLSI chips. The ORGA architecture is extremely robust for many failure modes caused by high-energy charged particles. Among such developments, dynamic optically reconfigurable gate arrays (DORGAs) have been developed to realize a high-gate-density VLSI using a photodiode memory architecture. Unfortunately, the DORGA architecture is more sensitive to the unallowable turn-off failure mode of a laser array. Therefore, this paper presents a 16-configuration-context dynamic optically reconfigurable gate array with a dependable laser array.

Influence analysis of a holographic memory window of a programmable optically reconfigurable gate array

Abstract: Recently, optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser array, have been developed to achieve a huge virtual gate count that is much larger than those of currently available VLSIs. However, comparison of conventional ORGAs with current field programmable gate arrays (FPGAs) reveals one important shortcoming: they are not reprogrammable after fabrication. To remove that shortcoming, a programmable ORGA (PORGA) has been proposed. However, a PORGA must implement a window to detect holographic memory patterns. A PORGA window might have scratches, fingerprints, or other defects that could occur while a PORGA is used. Even under such situations, a PORGA must be programmable. This paper therefore presents influence analysis of a holographic memory window of a PORGA. It has been demonstrated that even if a window of PORGA has scratches, fingerprint, or defects, a programming procedure can be executed correctly.

Micro-Coded Programmable Solution for a Class of OFDM Applications

Abstract: In modern communications systems, there is a growing need for programmability, yet cost pressures push towards full ASIC solutions. Our paper describes a common platform capable of implementing different OFDM-based computational requirements. This engine can compute Radix-2, and Radix-4 DFT and IDFT, Pre- twiddling and post twiddling, complex gain scaling and shift scaling. A novel technique for automatic overflow protection will be described, which reduces internal quantization effects. The complexity is much lower than that of a general purpose DSP and the gate count is comparable to full hardware implementation, yet the engine provides performance comparable to full hardware and programmability through the execution of microcode.

Experimental Results of Testing a BIST Σ–Δ ADC on the HOY Wireless Test Platform

Abstract: High pin count packaging and 3D IC technology make testing such advanced ICs more and more difficult and expensive. The HOY wireless test platform provides an alternative and cost-effective test solution to address the poor accessibility and high test cost issues. The key idea is implementing a low-cost and short-distance wireless transceiver on chip so that all test instructions and data can be transmitted without physical access. Due to the limited wireless bandwidth, all modules in the device under test (DUT) are preferred to have some built-in self-test (BIST) features. Prior works successfully demonstrated that DUTs with memory and digital circuits can be tested on the low-cost wireless test platform. However, there is no example to show if it is also possible to test the DUT embedded with analog circuits on the HOY test platform. This paper demonstrates the first system-level integration including hardware and software for testing a fully-integrated BIST ADC on the HOY wireless test platform. The DUT chip fabricated in 0.18-μm CMOS consists of a second-order Σ–Δ ADC under test (AUT) and the BIST circuitry. The AUT design employs the decorrelating design-for-digital-testability (D3T) scheme to make itself digitally testable. The BIST design is based on the modified controlled sine wave fitting (CSWF) method. The required BIST circuits are purely digital and as small as 9.9k gates. The gate count of the HOY test wrapper is less than 1k. Experimental results obtained by the HOY wireless test platform show that the AUT achieves a dynamic range of 85.1 dB and a peak SNDR of 78.6 dB. The wireless test results show good agreement with those acquired by conventional analog tests.

Optimization, FPGA Implementation & CMOS Realization of Reversible Shift Registers

Abstract: Recently reversible logic has emerged as one of the most important designs as it is known to provide zero power dissipation under ideal conditions. Reversible logic is used in the field of low power VLSI, nano technology, communications, high speed VLSI, digital signal processing etc. The optimization is carried out in reversible circuits by reducing gate count, constant inputs, garbage outputs as well as quantum cost. In this paper we are presenting the optimized designs of sequential circuits such as flip-flop and four types of shift registers in both FPGA implementation and CMOS implementation. In the cmos implementation we have used 180nm cmos technology in the design of shift registers. At final we obtained the results of power, delay and power delay product of shift registers using mosfet of 180nm technology.