Topic
Gate count
About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.
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01 Jan 2006
TL;DR: The DSP architecture, instruction set, and integrated programmable digital pulse width modulator have been optimized for digitally controlled switched mode power converters (SMPCs) and provides a programmable and cast effective solution for digitallycontrolled SMPCs.
Abstract: Abstmcf-This paper describes a novel and highly versatile reduced instruction set (RISC) based fixed point digital signal processor (DSP). Its architecture, instruction set, and integrated programmable digital pulse width modulator (DPWM) have been optimized for digitally controlled switched mode power converters (SMPCs). Designed using the Verilog hardware description language (HDL), the prototype DSP integrated circuit (IC) was built on a standard 0.35 pm digital CMOS process (with a 20 K gate count). It occupies less then 1.5 mm’ and dissipates approximately 5 mW from a 3.3 V supply at 50 MIPS. The device provides a programmable and cast effective solution for digitally controlled SMPCs.
20 Dec 2022
TL;DR: In this article , the authors present Reqomp, a method to automatically synthesize correct and efficient ancillae while respecting hardware constraints, which can offer a wide range of trade-offs between tightly constraining qubit count or gate count.
Abstract: Quantum circuits must run on quantum computers with tight limits on qubit and gate counts. To generate circuits respecting both limits, a promising opportunity is exploiting uncomputation to trade qubits for gates. We present Reqomp, a method to automatically synthesize correct and efficient uncomputation of ancillae while respecting hardware constraints. For a given circuit, Reqomp can offer a wide range of trade-offs between tightly constraining qubit count or gate count. Our evaluation demonstrates that Reqomp can significantly reduce the number of required ancilla qubits by up to 96%. On 80% of our benchmarks, the ancilla qubits required can be reduced by at least 25% while never incurring a gate count increase beyond 28%.
27 Jun 2022
TL;DR: TopAS as discussed by the authors is a topology aware synthesis tool built with the BQSKit framework that preconditions quantum circuits before mapping, which can be used to reduce the depth and gate count of wide quantum circuits.
Abstract: Unitary synthesis is an optimization technique that can achieve optimal multi-qubit gate counts while mapping quantum circuits to restrictive qubit topologies. Because synthesis algorithms are limited in scalability by their exponentially growing run time and memory requirements, application to circuits wider than 5 qubits requires divide-and-conquer partitioning of circuits into smaller components. In this work, we will explore methods to reduce the depth (program run time) and multi-qubit gate instruction count of wide (16-100 qubit) mapped quantum circuits optimized with synthesis. Reducing circuit depth and gate count directly impacts program performance and the likelihood of successful execution for quantum circuits on parallel quantum machines. We present TopAS, a topology aware synthesis tool built with the \emph{BQSKit} framework that preconditions quantum circuits before mapping. Partitioned subcircuits are optimized and fitted to sparse qubit subtopologies in a way that balances the often opposing demands of synthesis and mapping algorithms. This technique can be used to reduce the depth and gate count of wide quantum circuits mapped to the sparse qubit topologies of Google and IBM. Compared to large scale synthesis algorithms which focus on optimizing quantum circuits after mapping, TopAS is able to reduce depth by an average of 35.2% and CNOT gate count an average of 11.5% when targeting a 2D mesh topology. When compared with traditional quantum compilers using peephole optimization and mapping algorithms from the Qiskit or $t|ket\rangle$ toolkits, our approach is able to provide significant improvements in performance, reducing CNOT counts by 30.3% and depth by 38.2% on average.
18 Nov 2011
TL;DR: The redundant data in integer motion estimation that comes from overlapping reference blocks of consecutive current macro blocks processing is eliminated to reduce memory access rate and unique interpolation processing is employed to reduce the latency by half.
Abstract: In this paper, the redundant data in integer motion estimation that comes from overlapping reference blocks of consecutive current macro blocks processing is eliminated to reduce memory access rate. Based on early predicted candidate in fractional motion estimation, unique interpolation processing is employed to reduce the latency by half. In addition, based on high correlation, the scheme of processing 4×8 and 4×4 block with free of cycles is proposed, so that the number of motion vectors on FME can be reduced up to 59%. Experimental results show that the proposed motion estimation design saves 16% of gate count and 65% of local memory while supporting higher encoding specification.
01 Jan 2011
TL;DR: It can be concluded that on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure is an enabler in solving problems that affect communications capability in FFT and possesses huge potentials for future related works and research areas.
Abstract: The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This paper presents FPGA implementation of pipeline digit- slicing multiplier-less radix 2 2 DIF (Decimation In Frequency) SDF (single path delay feedback) butterfly for FFT structure. The approach taken; in order to reduce computation complexity in butterfly multiplier, digit-slicing multiplier-less technique was utilized in the critical path of pipeline Radix-2 2 DIF SDF FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The multiplier input data was sliced into four blocks each one with four bits to process at the same time in parallel. The new architecture was investigated and simulated with MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board. Consequently, the Virtex- II FG456 Proto board was used to implement and test the design on the real hardware. As a result, from the findings, the synthesis report indicates the maximum clock frequency of 555.75 MHz with the total equivalent gate count of 32,146 is a marked and significant improvement over Radix 2 2 DIF SDF FFT butterfly. In comparison with the conventional butterfly architecture design which can only run at a maximum clock frequency of 200.102 MHz and the conventional multiplier can only run at a maximum clock frequency of 221.140 MHz, the proposed system exhibits better results. It can be concluded that on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure is an enabler in solving problems that affect communications capability in FFT and possesses huge potentials for future related works and research areas.