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Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.


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Proceedings ArticleDOI
09 Jun 2008
TL;DR: This work illustrates a framework to build high-performance secure execution systems by embedding data for security and trust purposes by an instruction-block level data hiding technique, which can be used to defend against malicious attacks (such as Trojan injection).
Abstract: Recently, a novel data hiding technique was proposed to embed information into compiled binary codes in order to enhance system performance. Using this technique as a vehicle, we propose a framework to build high-performance secure execution systems by embedding data for security and trust purposes. We illustrate this approach in a mobile computing environment by an instruction-block level data hiding technique, which can be used to defend against malicious attacks (such as Trojan injection). This improves the trustworthiness of mobile codes. It also protects the code providerpsilas intellectual property because the code can be executed only on the designated device. When combined with the existing approach in [4], the proposed data hiding framework can provide trust and high-performance simultaneously. Finally, we conduct a proof-of-the-concept FPGA prototyping to validate the data hiding technique and evaluate the hardware cost in terms of gate count, power consumption, and gate delay.
Journal ArticleDOI
TL;DR: The OmniFlow processor can be used to provide a reliable transmission of UDP as well as TCP applications and only active flows can be effectively managed by terminating a flow that does not have a packet transmitted within this period.
Abstract: We propose a network processor called an OmniFlow processor capable of wire-speed flow management by a hardware-based flow admission control(FAC) in this paper. Because the OmniFlow processor can set up and release a wire-speed connection for flows, the update period of flows can be set to a short time, and only active flows can be effectively managed by terminating a flow that does not have a packet transmitted within this period. Therefore, the FAC can be used to provide a reliable transmission of UDP as well as TCP applications. This processor is fabricated in 65nm CMOS technology, and total gate count is 25 million. It has 40 Gb/s throughput performance in using the 32 RISC cores when maximum operating frequency is 555MHz.
Patent
08 Apr 2008
TL;DR: In this paper, a method and apparatus for efficiently performing digital signal processing is provided, in which kernel matrix computations are simplified by grouping similar kernel coefficients together, each coefficient group contains only coefficients having the same value.
Abstract: A method and apparatus for efficiently performing digital signal processing is provided. In one embodiment, kernel matrix computations are simplified by grouping similar kernel coefficients together. Each coefficient group contains only coefficients having the same value. At least one of the coefficient groups has at least two coefficients. Techniques are disclosed herein to efficiently apply successive first order difference operations to a data signal. The techniques allow for a low gate count. In particular, the techniques allow for a reduction of the number of multipliers without increasing clock frequency, in an embodiment. The techniques update pixels of a data signal at a rate of two clock cycles per each pixel, in an embodiment. The techniques allow hardware that is used to process a first pixel to be re-used to start the processing of a second pixel while the first pixel is still being processed.
Proceedings ArticleDOI
01 Nov 2007
TL;DR: This paper presents the design of a dynamic reconfigurable processor using an array of two dimensional logarithmic numbering system (LNS) processing elements and registers that configures dynamically during operation and executes the required task with different structures in each phase.
Abstract: This paper presents the design of a dynamic reconfigurable processor using an array of two dimensional logarithmic numbering system (LNS) processing elements and registers. By programming the processor, the array configures dynamically during operation and executes the required task with different structures in each phase. The proposed coarse grain array architecture is suitable for implementation of software radio baseband equalizers. Since redundant elements found in fine grained structures are reduced, the design consumes less chip area and power. Several different equalizer algorithms including the CMA for QPSK and BPSK signals, the finite interval CMA and the sliding window CMA equalizers are implemented and programmed on the proposed processor array and successive operation is shown. The architecture is designed in a 0.13 ?m CMOS technology and simulated for extraction of chip specifications. Power consumption, operation speed, gate count and chip area of the design are reported.
Proceedings Article
01 Jan 2011
TL;DR: In this paper, the authors presented an FPGA implementation of pipeline digit-slicing multiplier-less radix 2 2 DIF (Decimation In Frequency) SDF (single path delay feedback) butterfly for FFT structure.
Abstract: The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This paper presents FPGA implementation of pipeline digit-slicing multiplier-less radix 2 2 DIF (Decimation In Frequency) SDF (single path delay feedback) butterfly for FFT structure. The approach taken; in order to reduce computation complexity in butterfly multiplier, digit-slicing multiplier-less technique was utilized in the critical path of pipeline Radix-2 2 DIF SDF FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The multiplier input data was sliced into four blocks each one with four bits to process at the same time in parallel. The new architecture was investigated and simulated with MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board. Consequently, the Virtex-II FG456 Proto board was used to implement and test the design on the real hardware. As a result, from the findings, the synthesis report indicates the maximum clock frequency of 555.75 MHz with the total equivalent gate count of 32,146 is a marked and significant improvement over Radix 2 2 DIF SDF FFT butterfly. In comparison with the conventional butterfly architecture design which can only run at a maximum clock frequency of 200.102 MHz and the conventional multiplier can only run at a maximum clock frequency of 221.140 MHz, the proposed system exhibits better results. It can be concluded that on-chip implementation of pipeline digit-slicing multiplier-less butterfly for FFT structure is an enabler in solving problems that affect communications capability in FFT and possesses huge potentials for future related works and research areas.

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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20236
202219
202151
202047
201938
201847