Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

The Grain Family of Stream Ciphers

Abstract: A new family of stream ciphers, Grain, is proposed. Two variants, a 80-bit and a 128-bit variant are specified, denoted Grain and Grain-128 respectively. The designs target hardware environments where gate count, power consumption and memory are very limited. Both variants are based on two shift registers and a nonlinear output function. The ciphers also have the additional feature that the speed can be easily increased at the expense of extra hardware.

Toffoli network synthesis with templates

Abstract: Reversible logic functions can be realized as networks of Toffoli gates. The synthesis of Toffoli networks can be divided into two steps. First, find a network that realizes the desired function. Second, transform the network such that it uses fewer gates, while realizing the same function. This paper addresses the above synthesis approach. We present a basic method and, based on that, a bidirectional synthesis algorithm which produces a network of Toffoli gates realizing a given reversible specification. An asymptotically optimal modification of the basic synthesis algorithm employing generalized mEXOR gates is also presented. Transformations are then applied using template matching. The basis for a template is a network of gates that realizes the identity function. If a sequence of gates in the synthesized network matches a sequence comprised of more than half the gates in a template, then a transformation using the remaining gates in the template can be applied resulting in a reduction in the gate count for the synthesized network. All templates with up to six gates are described in this paper. Experimental results including an exhaustive examination of all 3-variable reversible functions and a collection of benchmark problems are presented. The paper concludes with suggestions for further research.

Techniques for the synthesis of reversible Toffoli networks

Abstract: We present certain new techniques for the synthesis of reversible networks of Toffoli gates, as well as improvements to previous methods. Gate count and technology oriented cost metrics are used. Two new synthesis procedures employing Reed-Muller spectra are introduced and shown to complement earlier synthesis approaches. The previously proposed template simplification method is enhanced through the introduction of a faster and more efficient template application algorithm, an updated classification of the templates, and the addition of new templates of sizes 7 and 9. A resynthesis approach is introduced wherein a sequence of gates is chosen from a network, and the reversible specification it realizes is resynthesized as an independent problem in hopes of reducing the network cost. Empirical results are presented to show that the methods are efficient in terms of the realization of reversible benchmark specifications.

A new combinational logic minimization technique with applications to cryptology

Abstract: A new technique for combinational logic optimization is described. The technique is a two-step process. In the first step, the non-linearity of a circuit – as measured by the number of non-linear gates it contains – is reduced. The second step reduces the number of gates in the linear components of the already reduced circuit. The technique can be applied to arbitrary combinational logic problems, and often yields improvements even after optimization by standard methods has been performed. In this paper we show the results of our technique when applied to the S-box of the Advanced Encryption Standard (AES [6]). This is an experimental proof of concept, as opposed to a full-fledged circuit optimization effort. Nevertheless the result is, as far as we know, the circuit with the smallest gate count yet constructed for this function. We have also used the technique to improve the performance (in software) of several candidates to the Cryptographic Hash Algorithm Competition. Finally, we have experimentally verified that the second step of our technique yields significant improvements over conventional methods when applied to randomly chosen linear transformations.

Gate-based single-shot readout of spins in silicon.

Abstract: Electron spins in silicon quantum dots provide a promising route towards realizing the large number of coupled qubits required for a useful quantum processor1-7. For the implementation of quantum algorithms and error detection8-10, qubit measurements are ideally performed in a single shot, which is presently achieved using on-chip charge sensors, capacitively coupled to the quantum dots11. However, as the number of qubits is increased, this approach becomes impractical due to the footprint and complexity of the charge sensors, combined with the required proximity to the quantum dots12. Alternatively, the spin state can be measured directly by detecting the complex impedance of spin-dependent electron tunnelling between quantum dots13-15. This can be achieved using radiofrequency reflectometry on a single gate electrode defining the quantum dot itself15-19, significantly reducing the gate count and architectural complexity, but thus far it has not been possible to achieve single-shot spin readout using this technique. Here, we detect single electron tunnelling in a double quantum dot and demonstrate that gate-based sensing can be used to read out the electron spin state in a single shot, with an average readout fidelity of 73%. The result demonstrates a key step towards the readout of many spin qubits in parallel, using a compact gate design that will be needed for a large-scale semiconductor quantum processor.