Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

A single-chip FPGA design for real-time ICA-based blind source separation algorithm

Abstract: Blind source separation (BSS) of independent sources from their mixtures is a common problem in real world multi-sensor applications. In this paper, we propose an efficient hardware architecture for the implementation of real-time BSS that can be implemented using a low-cost FPGA. The architecture offers a good balance between hardware requirement (gate count and minimal clock speed) and separation performance. The FPGA design implements the modified Torkkola BSS algorithm for audio signals based on the ICA (independent component analysis) technique. The separation is performed by implementing noncausal filters, instead of the typical causal filters, within the feedback network. The architecture of the hardware is described. Results of various FPGA simulations and real-time testing of the final hardware design in a real environment are given.

Efficient FPGA implementation of an adaptive noise canceller

Abstract: A hardware implementation of an adaptive noise canceller (ANC) is presented. It has been synthesized within an FPGA, using a modified version of the least mean square (LMS) error algorithm. The results obtained so far show a significant decrease of the required gate count when compared with a standard LMS implementation, while increasing the ANC bandwidth and signal to noise (S/N) ratio. This novel adaptive noise canceller is then useful for enhancing the S/N ratio of data collected from sensors (or sensor arrays) working in noisy environment, or dealing with potentially weak signals.

VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems

Abstract: This paper presents the VLSI design of a reconfigurable multimode Reed Solomon (RS) codec for various high-speed communication systems. Our decoder design is based on the Euclidean algorithm such that the datapath units are regular and simple. With its ability to support a variety of (n, k, t) RS specifications (0/spl les/t/spl les/8) and (0/spl les/n/spl les/255), this RS codec design is suitable for multi-mode systems such as the xDSL and the cable modem systems. The chip operates at a clock frequency of 100 MHz and has a data processing rate of 800 Mbits/s in 0.35 /spl mu/m CMOS technology at the supply voltage of 3.3 V. The total gate count is 34,647 gates and the core size is only 1,578 /spl times/ 1,560 /spl mu/m/sup 2/.

Smashing the Implementation Records of AES S-box

Abstract: Canright S-box has been known as the most compact S-box design since its introduction back in CHES’05. Boyar-Peralta proposed logic-minimization heuristics that could reduce the gate count of Canright S-box from 120 gates to 113 gates, however synthesis results did not reflect much improvement. In CHES’15, Ueno et al. proposed an S-box that has a slightly higher area, but significantly faster than the previous designs, hence it was the most efficient (measured by area×delay) S-box implementation to date. In this paper, we propose two new designs for the AES S-box. One design has a smaller implementation area than both Canright and the 113-gate S-boxes. Hence, our first design is the smallest AES S-box to date, breaking the 13 years implementation record of Canright. The second design is faster and smaller than the Ueno S-box. Hence, our second design is both the fastest and the most efficient S-box design to date. While doing so, we also propose new logicminimization heuristics that outperform the previous algorithms of Boyar-Peralta. Finally, we conduct an exhaustive evaluation of each and every block in the S-box circuit, using both structural and behavioral HDL modeling, to reach the optimum synergy between theoretical algorithms and technology-supported optimization tools. We show that involving the technology-supported CAD tools in the analysis results in several counter-intuitive results.

An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC

Abstract: In this paper, we present an efficient architecture for deblocking filter in H.264/AVC. A novel 2-dimensional parallel memory scheme is employed in order to achieve highly efficient parallel access in both horizontal and vertical directions. By using this parallel memory scheme, we also eliminate the need for a transpose circuit. Our design is implemented under 0.35/spl mu/m technology. Synthesis results show that the equivalent gate count is only 9.35K (not including SRAMs) when the maximum frequency is 100MHz.