Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices

Abstract: According to large-page-size and random-bit-error characteristics, long-block-length Bose-Chaudhuri-Hochquenghem (BCH) decoders are applied to realize error correction in NAND Flash memory devices. To accelerate the decoding process in an area-efficient architecture, a parallel architecture with minimal polynomial combinational network (MPCN) for long BCH decoders is presented in this brief. The proposed design utilizes MPCNs to replace constant finite-field multipliers, which dominate the hardware complexity of the high-parallel Chien search architecture. Furthermore, both the syndrome calculator and the Chien search can be merged by exploiting our MPCN-based architecture, leading to significant hardware complexity reduction. From the synthesis results in the 90-nm CMOS technology, the MPCN-based joint syndrome calculation and Chien search has 46.7% gate count saving for parallel-32 BCH (4603, 4096; 39) decoder in contrast with the straightforward design.

Minimization of Logic Networks Under a Generalized Cost Function

Abstract: Based on the intuitive observation that smaller numbers of gates and connections would usually lead to a more compact network on an integrated circuit (IC), a monotonically increasing function of gate count and connection count is concluded to be a reasonable cost function to be minimized in the logical design of a network implemented in IC. Then it is shown that all minimal solutions of such a cost function always can be found among the following: minimal networks with a minimal number of gates as the first objective and a minimal number of connections as the second objective; minimal networks with a minimal number of connections as the first objective and a minimal number of gates as the second objective; and minimal networks which are associated with the above two types of minimal networks. All three of these types of minimal networks of NOR gates, as an example, are calculated by logical design programs based on integer programming, for all functions of 3 or less variables and also some functions of 4 variables which require 5 or less NOR gates. According to the computational results, for the majority of the functions the first type of minimal networks is identical to the second type, and for no function were networks of the third type found to exist.

High-level area and power estimation for VLSI circuits

Abstract: This paper addresses the problem of computing the area complexity of a multi-output combinational logic circuit, given only its functional description, i.e., Boolean equations, where area complexity is measured in terms of the number of gates required for an optimal multilevel implementation of the combinational logic. The proposed area model is based on transforming the given, multi-output Boolean function description into an equivalent single-output function. The model, is empirical, and results demonstrating its feasibility and utility are presented. Also, a methodology for converting the gate count estimates, obtained from the area model, into capacitance estimates is presented. High-level power estimates based on the total capacitance estimates and average activity estimates are also presented.

Computer-Aided Synthesis or Multiple-Output Multilevel NAND Networks witk Fan-in and Fan-out Constraints

Abstract: A straightforward efficient computer algorithm for synthesizing multiple-output NAND (NOR) switching networks is presented which takes practical fan-in and fan-out limitations of logic gates into account. The algorithm is highly iterative and hence is very suitable for realizing large-size switching functions by a digital computer. The algorithm has been programmed in Fortran and a great deal of statistical data has been obtained to demonstrate its efficiency in terms of gate count as well as computing time. It is also efficient for hand execution

A Low-Power Parallel Architecture for Linear Feedback Shift Registers

Abstract: Linear feedback shift registers (LFSRs) are used to implement BCH encoders and cyclic redundancy check (CRC), which are broadly used in digital communication systems. Previous parallel LFSR designs adopt a state-space transformation that shortens the feedback data path and reduces the gate count. Transformations have been designed to minimize the total gate count of the three involved matrix multiplications. However, the transformation matrix multiplication is only active for one clock cycle at the end. In this brief, we propose an alternative transformation matrix construction that effectively shifts the complexity from the other two matrices, which are active in every clock cycle, to the transformation matrix without increasing the critical path or the total gate count. For an example CRC-32, the proposed design achieves 33% power and 8% gate count reductions without compromising the achievable clock frequency.