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Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.


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Proceedings ArticleDOI
26 May 2010
TL;DR: A new algorithm MP(multiple pass) to synthesize large reversible binary circuits without ancilla bits is presented, which allows for synthesis of large scale reversible circuits (30-bits), which is not possible with existing algorithms.
Abstract: This paper presents a new algorithm MP(multiple pass) to synthesize large reversible binary circuits without ancilla bits. The MMD algorithm requires to store a truth table (or a Reed-Muller -RM transform) as a 2^n vector for a reversible function of n variables. This representation prohibits synthesis of large functions. However, in MP we do not store such an exponentially growing data structure. The values of minterms are calculated in MP dynamically, one-by-one, from a set of logic equations that specify the reversible circuit to be designed. This allows for synthesis of large scale reversible circuits (30-bits), which is not possible with existing algorithms. In addition, our unique multipass approach where the circuit is synthesized with various, yet specific, minterm orders yields optimal solution. The algorithm returns a description of the optimal circuit with respect to gate count or quantum cost. Although the synthesis process is relatively slower, the solution is found in real-time for smaller circuits of 8 bits or less

20 citations

Patent
28 Feb 2003
TL;DR: In this article, an improved WLAN solution for embedded systems incorporating optimized partitioning; it reduces power consumption and systems cost by up to 50%. All silicon gates associated with the redundant RISC processor, redundant SRAM and flash memories used in prior art WLAN solutions are eliminated.
Abstract: An improved WLAN solution for embedded systems incorporating optimized partitioning; it reduces power consumption and systems cost by up to 50%. All silicon gates associated with the redundant RISC processor, redundant SRAM and flash memories used in prior art WLAN solutions are eliminated. The invention includes a low gate count PHY Accelerator ASIC, a dual core processor (DCP), a portion of the PHY in software, and an innovative software MAC architecture supported by minimal hardware acceleration. The DCP is a standard off-the-shelf component incorporating DSP and RISC processors. It executes software portions of the MAC and PHY. The DCP communicates with the PHY Accelerator through a novel parallel interface that improves throughput while reducing processing requirements on DCP. Also, the PHY accelerator, or certain portions of it, may be embedded into the DCP. Invention includes a novel “resource utilization scheme”, whereby the various DCP resources get judiciously re-deployed.

20 citations

Proceedings ArticleDOI
24 Oct 2008
TL;DR: High throughput architecture of an encoder and a decoder for a quasi-cyclic low-density parity-check (LDPC) code and a new systematic encoding method carried out by polynomial manipulation are proposed.
Abstract: High throughput architecture of an encoder and a decoder for a quasi-cyclic low-density parity-check (LDPC) code is proposed. A new systematic encoding method is carried out by polynomial manipulation. The proposed decoder architecture, where the check-node process is split into two processes so that the memory access becomes column-wise, enables overlapped message-passing for any parity-check matrix. The hardware architecture for the check-node processes utilizing a quasi-cyclic structure does not require complex multiplexers. Hardware employing the proposed architecture for a (1440,1344) LDPC code designed for high throughput millimeter wave application is evaluated using 65 nm CMOS technology. The gate count of the encoder for 3 Gbps and 6 Gbps throughput is 2.5 k and 3.1 k, respectively, and the gate count of the decoder for 8 iterations is 304 k and 409 k, respectively. A bit-error rate of 10-6 is obtained at Eb/N0 of 5.9 dB, and the estimated power consumption of the decoder is 58 mW for 3 Gbps and 86 mW for 6 Gbps.

20 citations

Journal ArticleDOI
TL;DR: In this article, the authors studied the use of global entangling operations to improve the entangling gate count in circuits composed with global Ising entangling gates and arbitrary addressable single-qubit gates.
Abstract: In this paper we study the ways to use a global entangling operator to efficiently implement circuitry common to a selection of important quantum algorithms. In particular, we focus on the circuits composed with global Ising entangling gates and arbitrary addressable single-qubit gates. We show that under certain circumstances the use of global operations can substantially improve the entangling gate count.

20 citations

Journal ArticleDOI
TL;DR: This paper aims at furnishing a proposed DC gate (DC stands for decoder comparator) to help the construction of these mentioned circuits, and a new concept of the quantum equivalent of combined reversible gates is presented by the algorithm.
Abstract: In this era of emerging technology, reversible logic is applied for circuit design. Due to the deep submicron and scaling, a number of pitfalls are faced by the CMOS technology. So a lot of constraints related to CMOS are stated with the QCA technology. The aim of this paper is the efficient conservative reversible decoder circuit design with optimal reversible metrics. It aims at furnishing a proposed DC gate (DC stands for decoder comparator) to help the construction of these mentioned circuits. Finally, the DC is employed to construct the n-bit reversible decoder. Moreover, a new concept of the quantum equivalent of combined reversible gates is presented by the algorithm. By the comparative outcomes, it is found that the proposed decoder had achieved 25% quantum cost, 66% gate count, and 50% garbage outputs as compared to the counterpart. Further, stuck-at-fault for the single- and multiple-bit input and output is applied to the DC gate for testability. Moreover, the DC gate in the physical foreground ...

20 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20236
202219
202151
202047
201938
201847