Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

Improved FFSBM algorithm and its VLSI architecture for variable block size motion estimation of H.264

Abstract: The video coding standard H264/AVC has adopted variable block size motion estimation to improve coding efficiency, which has brought heavy computation burden The FFSBM (fast full search block matching) algorithm has been proposed to reduce the complexity This paper proposes an improved FFSBM to adaptively reduce the complexity of FFSBM according to the degree of motion activity A modular 2-D VLSI architecture to implement the improved algorithm is also proposed, the size of the PE array is carefully selected to reduce the gate count Experimental result shows that this algorithm-hardware co-design gives better area/throughput tradeoff than the existing ones and is a proper solution for H264's variable block size motion estimation

Comment on "When to Use Random Testing"

Abstract: This correspondence indicates a weakness in forming the criteria used to decide when random testing is practical. The use of average fan-in based on total gate count is an oversimplification and results in too low a threshold for use of random testing in lieu of a complete test of 2N patterns. A modification is given to avoid this difficulty.

Efficient parallel implementation of reservoir computing systems

Abstract: Reservoir computing (RC) is a powerful machine learning methodology well suited for time-series processing. The hardware implementation of RC systems (HRC) may extend the utility of this neural approach to solve real-life problems for which software solutions are not satisfactory. Nevertheless, the implementation of massive parallel-connected reservoir networks is costly in terms of circuit area and power, mainly due to the requirement of implementing synapse multipliers that increase gate count to prohibitive values. Most HRC systems present in the literature solve this area problem by sequencializing the processes, thus loosing the expected fault-tolerance and low latency of fully parallel-connected HRCs. Therefore, the development of new methodologies to implement fully parallel HRC systems is of high interest to many computational intelligence applications requiring quick responses. In this article, we propose a compact hardware implementation for Echo-State Networks (an specific type of reservoir) that reduces the area cost by simplifying the synapses and using linear piece-wise activation functions for neurons. The proposed design is synthesized in a Field-Programmable Gate Array and evaluated for different time-series prediction tasks. Without compromising the overall accuracy, the proposed approach achieves a significant saving in terms of power and hardware when compared with recently published implementations. This technique pave the way for the low-power implementation of fully parallel reservoir networks containing thousands of neurons in a single integrated circuit.

Configurable Pipelined Gabor Filter implementation for fingerprint image enhancement

Abstract: In this paper a novel Gabor filter hardware scheme for the fingerprint image enhancement is presented. For each pixel of the image, we use accurate local frequency and orientation to generate the corresponding convolution kernel and thus achieve a better enhancement effect. And compared to the previous works, our design yields a higher throughput which is due to the pipeline techniques. Moreover the proposed design can be reconfigured to fulfill the different requirements. Evaluation results demonstrate that, when convolution kernel size is 11×11, our design can achieve 2MPixels/s @ 250MHz, and equivalent gate count is 63.8k at SMIC 0.13um worst process corner. Indeed, it's very suitable for the embedded fingerprint recognition system.

Logic Design Validation via Simulation and Automatic Test Pattern Generation

Abstract: We investigate an automated design validation scheme for gate-level combinational and sequential circuits that borrows methods from simulation and test generation for physical faults, and verifies a circuit with respect to a modeled set of design errors. The error models used in prior research are examined and reduced to five types: gate substitution errors (GSEs), gate count errors (GCEs), input count errors (ICEs), wrong input errors (WIEs), and latch count errors (LCEs). Conditions are derived for a gate to be testable for GSEs, which lead to small, complete test sets for GSEss near-minimal test sets are also derived for GCEs. We analyze undetectability in design errors and relate it to single stuck-line (SSL) redundancy. We show how to map all the foregoing error types into SSL faults, and describe an extensive set of experiments to evaluate the proposed method. These experiments demonstrate that high coverage of the modeled errors can be achieved with small test sets obtained with standard test generation and simulation tools for physical faults.