Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

Device and method for efficient timing estimation in a digital receiver

Abstract: The present invention provides for economical predictive symbol timing estimation in a digital receiver by reducing gate count and current drain. The invention also reduces the processing delay. The predictive symbol timing estimation method (300) and device (200) are applicable to any digital radio system which transmits on a continuous or semi-continuous basis.

Effective RT-level software-based self-testing of embedded processor cores

Abstract: Embedded processors are often used in systems that are both safety-critical and long-living. Therefore testing of these devices is critical not only after production, but also in the field. Due to the limited accessibility of embedded processors, testing of such systems is a major challenge in terms of ultra-deep submicron issues. Scan based testing methods cannot be applied to embedded processor cores which cannot be modified to meet the design requirements for scan insertion. From the other side, generating test vectors for these high gate count devices is a major task. This paper presents a high level, component-oriented software-based self-testing method which achieves a high stuck-at-fault coverage for an embedded processor core. The method requires no DFT or changing the processor architecture. The proposed method is high level in the sense that it is based on the knowledge of the Instruction Set Architecture (ISA) and Register Transfer Level (RTL) description of the processor. The method is well suited for meeting the challenges of testing SoCs which contain embedded processor cores. Our methodology is superior in terms of test quality in such a way that significantly increases fault coverage and reduces test time. The proposed method outperforms all existing method in terms of fault coverage.

Cost-performance analysis of FPGA, VLSI and WSI implementations of a RAM-based neural network

Abstract: The paper analyses the hardware implementation of a probabilistic RAM based neural network architecture, named HyperNet in terms of system training speed, size, and component cost. All the systems presented include on-board reinforcement training logic and the necessary control and interface circuitry. Circuit area, gate count, and speed figures are extrapolated from a 10,240 neuron custom VLSI based system constructed at the University of Hertfordshire in 1993. Varying degrees of parallelism, and three implementation technologies are considered. A palm-sized system with a single Xilinx 4025 FPGA serial processor can deliver approximately 800 times the performance of a Sun SPARCstation 10 at a cost of less than #1000. A double Eurocard sized custom VLSI based fully parallel system costs of the order of #10K and offers over five orders of magnitude training speed improvement over a Sun SPARCstation 10.

A universal VLSI architecture for bit-parallel computation in GF(2/sup m/)

Abstract: An universal VLSI architecture for bit-parallel computation in GF(2/sup m/) is presented The proposed architecture is based on Montgomery multiplication algorithm, which is suitable for multiple class of GF(2/sup m/) with arbitrary field degree m Due to the highly regular and modular property, our proposed universal architecture can meet VLSI design requirement After implemented by 018/spl mu/m 1P6M process, our universal architecture can work successfully at 125MHz clock rate For the finite field multiplier, the total gate count is 14K for GF(2/sup m/) with any irreducible polynomial of field degree m/spl les/8, whereas the inverse operation can be achieved by the control unit with gate count of 03K

Analysis and Hardware Architecture Design of Global Motion Estimation

Abstract: Global motion estimation and compensation (GME/GMC) is an important video processing technique and has been applied to many applications including video segmentation, sprite/mosaic generation, and video coding. In MPEG-4 Advanced Simple Profile (ASP), GME/GMC is adopted to compensate camera motions. Since GME is important, many GME algorithms have been proposed. These algorithms have two common characteristics, huge computation complexity and ultra large memory bandwidth. Hence for realtime applications, a hardware accelerator of GME is required. However, there are many hardware design challenges of GME like irregular memory access and huge memory bandwidth, and only few hardware architectures have been proposed. In this paper, we first analyzed three typical algorithms of GME, and a fast GME algorithm is proposed. By using temporal prediction and skipping the redundant computation, 91% memory bandwidth and 80% iterations are saved, while the performance is kept, compared to Gradient Descent in MPEG-4 Verification Model. Based on our proposed algorithm, a hardware architecture of GME is also presented. A new scheduling, Reference-Based Scheduling, is developed to solve the irregular memory access problem. An interleaved memory arrangement is applied to satisfy the memory access requirement of interpolation. The total gate count of hardware implementation is 131 K with Artisan 0.18 um cell library, and the internal memory size is about 7.9 Kb. Its processing ability is MPEG-4 ASP@L3, which is 352×288 with 30 fps, at 30 MHz.