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Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.


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Proceedings ArticleDOI
23 May 2004
TL;DR: Performance comparisons show that the number of clock cycles can be reduced about 40%/spl sim/80% for scrambling, convolutional encoding and interleaving compared with existing DSPs.
Abstract: This paper proposes application-specific instructions and their bit manipulation unit (BMU), which efficiently support scrambling, convolutional encoding, puncturing, and interleaving. The proposed DSP employs the BMU supporting parallel shift and XOR (Exclusive-OR) operations and bit insertion/extraction operations on multiple data. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18 /spl mu/m standard cell library and the gate count of the BMU is only about 1700 gates. Performance comparisons show that the number of clock cycles can be reduced about 40%/spl sim/80% for scrambling, convolutional encoding and interleaving compared with existing DSPs.

10 citations

Proceedings Article
01 Dec 2009
TL;DR: In this article, a low-complexity and full-mode BCH decoder with long block length for DVB-S2 application is presented with the reversed error locator polynomial.
Abstract: In this paper, a low-complexity and full-mode BCH decoder with long block length for DVB-S2 application is presented With the reversed error locator polynomial, our proposed reversed Berlekamp-Massey algorithm features a sharing architecture to perform parallel-4 syndrome and Chien search calculations Concatenated with the LDPC decoder, which has a long decoding latency and a short period of data output time, the proposed parallel-4 BCH decoder ensures the sufficient throughput with only one bank memory Moreover, a composite field divider instead of a large Galois field inversion table is also presented to reduce complexity After implemented in 013µm CMOS technology, our parallel-4 BCH decoder occupied 44K gate count can reach 380Mb/s according to the post-layout simulations

10 citations

Posted Content
TL;DR: A systematic procedure is used to obtain optimized circuits (circuits having reduced gate count and number of levels) for a large number of Clifford+T circuits which have already been implemented in the IBM quantum computers.
Abstract: Recently, various quantum computing and communication tasks have been implemented using IBM's superconductivity-based quantum computers which are available on the cloud. Here, we show that the circuits used in most of those works were not optimized and the use of the optimized circuits can considerably improve the possibility of observing unique features of quantum mechanics. Specifically, a systematic procedure is used here to obtain optimized circuits (circuits having reduced gate count and number of levels) for a large number of Clifford+T circuits which have already been implemented in the IBM quantum computers. Optimized circuits implementable in IBM quantum computers are also obtained for a set of reversible benchmark circuits. With a clear example, it is shown that the reduction in circuit costs enhances the fidelity of the output state (with respect to the theoretically expected state in the absence of noise) as lesser number of gates and levels introduce lesser amount of errors during evolution of the state. Further, considering Mermin inequality as an example, it's shown that the violation of classical limit is enhanced when we use an optimized circuit. Thus, the approach adopted here can be used to identify relatively weaker signature of quantumness and also to establish quantum supremacy in a stronger manner.

10 citations

Dissertation
01 Jan 2000
TL;DR: The purpose of this thesis is to develop this framework for orientation and photogrammetry systems for FPGAs by tailoring the algorithms, architectures, and precisions to fit into an FPGA.
Abstract: There is great demand today for real-time computer vision systems, with applications including image enhancement, target detection and surveillance, autonomous navigation, and scene reconstruction. These operations generally require extensive computing power; when multiple conventional processors and custom gate arrays are inappropriate, due to either excessive cost or risk, a class of devices known as Field-Programmable Gate Arrays (FPGAs) can be employed. FPGAs offer the flexibility of a programmable solution and nearly the performance of a custom gate array. When implementing a custom algorithm in an FPGA, one must be more efficient than with a gate array technology. By tailoring the algorithms, architectures, and precisions, the gate count of an algorithm may be sufficiently reduced to fit into an FPGA. The challenge is to perform this customization of the algorithm, while still maintaining the required performance. The techniques required to perform algorithmic optimization for FPGAs are scattered across many fields; what is currently lacking is a framework for utilizing all these well known and developing techniques. The purpose of this thesis is to develop this framework for orientation and photogrammetry systems. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.)

10 citations

Journal ArticleDOI
TL;DR: This paper illustrates a cost-effective, energy-efficient Universal Reversible Logic Gate in QCA framework which is capable of designing power analysis attack resistable hardware cryptographical circuit.
Abstract: Quantum-dot cellular automata (QCA) technology leads to rapid high-density combinatory low power exploitation to realize the reversible logic circuit in the nanoscale era. Reversible logic is an alternative to overcome excess energy indulgence of irreversible process. This paper illustrates a cost-effective, energy-efficient Universal Reversible Logic Gate in QCA framework which is capable of designing power analysis attack resistable hardware cryptographical circuit. The proposed (URLGs: U1 and U2) has been tested with simulator QCADesigner V2.0.3, outshined the existing pattern relating to the area, gate count, garbage count, and quantum cost. We found 37.5% garbage minimization is achieved compared to NFT, which is utmost minimization of garbage ever reported in QCA literature. Thirteen three variable standard Boolean functions are considered as logic benchmarks to guesstimate the capability and efficiency of proposed URLG in QCA circuit implementation and synthesizing logic gates. In average, our proposed U2 achieved 36.66% improvement in energy dissipation for different kink energy ratios over early reported work.

9 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20236
202219
202151
202047
201938
201847