Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

Asymptotically improved circuit for a <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>d</mml:mi></mml:math> -ary Grover's algorithm with advanced decomposition of the <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>n</mml:mi></mml:math> -qudit Toffoli gate

Abstract: The progress in building quantum computers to execute quantum algorithms has recently been remarkable. Grover's search algorithm in a binary quantum system provides a considerable speed-up over the classical paradigm. It can be extended to a $d$-ary (qudit) quantum system also for utilizing the advantage of larger state space, which helps to reduce the runtime of the algorithm as compared to the traditional binary quantum systems. In a qudit quantum system, an $n$-qudit Toffoli gate plays a significant role in the accurate implementation of Grover's algorithm. In this article, a generalized $n$-qudit Toffoli gate is realized using higher-dimensional qudits to attain a logarithmic depth decomposition without ancilla qudit. The circuit for Grover's algorithm has then been designed for any $d$-ary quantum system, where $d\ensuremath{\ge}2$, with the proposed $n$-qudit Toffoli gate to obtain optimized depth compared to earlier approaches. The technique for decomposing an $n$-qudit Toffoli gate requires access to two immediately higher-energy levels, making the design susceptible to errors. Nevertheless, we show that the percentage decrease in the probability of error is significant with both gate count and circuit depth reduced as compared to that in state-of-the-art works.

High-speed low-complexity architecture for reed-solomon decoders

Abstract: This paper presents a high-speed, low-complexity VLSI architecture based on the modified Euclidean (ME) algorithm for Reed-Solomon decoders. The low-complexity feature of the proposed architecture is obtained by reformulating the error locator and error evaluator polynomials to remove redundant information in the ME algorithm proposed by Truong. This increases the hardware utilization of the processing elements used to solve the key equation and reduces hardware by 30.4%. The proposed architecture retains the high-speed feature of Truong's ME algorithm with a reduced latency, achieved by changing the initial settings of the design. Analytical results show that the proposed architecture has the smallest critical path delay, latency, and area-time complexity in comparison with similar studies. An example RS(255, 239) decoder design, implemented using the TSMC 0.18µm process, can reach a throughput rate of 3Gbps at an operating frequency of 375MHz and with a total gate count of 27, 271.

A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications

Abstract: This article proposes a low-cost, low-power multistandard video decoder for high definition (HD) video applications. The proposed design supports multiple-standard (JPEG baseline, MPEG-1/2/4 Simple Profile (SP), and H.264 Baseline Profile (BP)) video decoding through interactive parsing control and common parameter bus interface. In order to reduce hardware cost, the shared adder-based structure and reusable data management are proposed to achieve hardware sharing and reduce internal memory size, respectively. In addition, the proposed design is optimized through reducing memory bandwidth by increasing both data reuse amount and burst length of memory access as well as eliminating cycle overhead in data access for supporting HD video decoding with single AHB-based SDR memory. The proposed 252Kgates/4.9kB/71mW/0.13μm multi-standard video decoder reduces 72p in gate count and 87p in power consumption as compared to the state-of-the-art design, when operating at 120MHz for real-time HD1080 video decoding with single AHB-based SDR memory.

Design of High-Speed Reconfigurable Coprocessor for Next-Generation Communication Platform

Abstract: In this paper, we present the high-speed reconfigurable coprocessor for the next-generation communication system, which is highly reliable and more accurate with less delay. The proposed high-speed reconfigurable coprocessor can be easily implemented using various standard operations such as bit shuffle operation, convolutional encoding, fast Fourier transform, interleaving, modulation, scrambling, shift-XOR array, Viterbi decoding, and several other function using the proposed design. The coprocessor has been modeled using VHDL, and synthesis has been performed on model-sim. The gate count is of about 34,000 and critical path of about 0:16 μm technology. The performance comparisons shows that the number of clock cycles can be reduced about 48 % for scrambling and 84 % for convolutional encoding compared with existing DSPs. From the results, the performance of the proposed coprocessor is better compared to conventional DSP (SC140) in terms of number of clocks per cycle.

A 333 ps/800 MHz 7 K-gate bipolar macrocell array employing 4 level metallization

Abstract: An ECL100K-compatible, bipolar, subnanosecond macrocell array has been developed. A new macrocell structure is proposed, using a 2-/spl mu/m design rule and four-level metallization SST-2 process. A basic macrocell consisting of 10 transistors and 12 resistors is formed by the stretched Pt-Si patterns for the electrodes of base and resistor. The basic circuit structure is a two-level series-gated ECL circuit with emitter-follower output. The high performance of the 333 ps/cell and an 800-MHz toggle frequency of a master-slave flip-flop were achieved using a 0.2-mA switching current. The gate count of the chip is equivalent to 6.8 to 8.3K gates.