Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

Design of Reversible Finite Field Arithmetic Circuits with Error Detection

Abstract: Motivated by the potential of reversible computing, we present a systematic method for the designing reversible arithmetic circuits for finite field or Galois fields of form GF(2m) It is shown that an adder over GF(2m) can be designed with m garbage bits and that of a PB multiplier with 2m garbage bits To tackle the problem of errors in computation, we also extend the circuit with error detection feature Gate count and technology oriented cost metrics are used for evaluation The expression for the upper bound for gate size is also derived for special primitive polynomials Our technique, when compared with existing CAD tool gives the same gate size and quantum cost

An embedded DSP core for wireless communication

Abstract: This paper proposes an embedded DSP core for communication applications with targets of demodulation/synchronization operation. Besides providing a basic instruction set, similar to current day 16-bit DSP processors, it contains distinguish instructions, and special function blocks like dual MAC, sub-word multiplier, dedicated FIR filter and multi-levels slicer, which make this DSP processor more efficient for several communication tasks. Also, the entire architecture is parameterized such that it can be embedded in a variety of applications. In the design of the chip, we adapt gray coded addressing for lowering switching activity, pipeline register sharing for reducing pipeline register and the entire architecture is used to reduce power dissipation. The DSP chip is implemented by synthesizable Verilog code with TSMC 0.35 /spl mu/m SPQM cell library. The equivalent gate count of the core without memory is about 50 k. The chip area is 4.10 mm*4.10 mm (with on chip memory).

Embedded tutorial: Applications of reversible logic in cryptography and coding theory

Abstract: Summary form only given, as follows. With the increasing emphasis on low-power design and quantum computation, research activities in the area of reversible logic synthesis and testing have gained momentum over the last couple of decades. It is expected that reversible logic will provide us with a viable alternative to building ultra-low power circuits and systems in not too distant future. In the classical works for synthesis of reversible circuits, gate libraries comprising of standard reversible gates like NOT, CNOT, TOFFOLI, FREDKIN, etc. are considered. To evaluate the goodness of a synthesized netlist, various metrics such as gate count, quantum cost, and equivalent transistor cost have been considered by various researchers. The synthesis approaches that have been reported can be broadly categorized into three groups: (a) exact synthesis approaches which try to obtain optimal reversible gate netlists, but can be used for small circuits only, (b) heuristic based approaches which try to utilize some domain knowledge intelligently to reduce the complexity of search, and can be used for somewhat larger circuits, and (c) synthesis approaches that rely on higher level functional representations like binary decision diagram (BDD) or exclusive sum-ofproducts (ESOP). The last approach is scalable to larger circuits (with 200 inputs or more), however, the synthesized netlist is not optimal and various rule-based heuristic approaches have been proposed to minimize the cost. There have been works also that report techniques for implementing sequential circuits with reversible properties, which will be useful for building complex systems containing finite-state machines. There are various transformations that are carried out as part of cryptographic algorithms that are inherently reversible in nature. For instance, any block cipher that uses a key K to transform a plaintext P into a ciphertext C during encryption must be reversible, because decryption will be doing just the reverse (C to P). Also, in standard symmetric block ciphers like DES or AES, there is a combinational block called substitution box or S-box which is also reversible in nature. In AES, the S-box has 8 inputs and 8 outputs, and implements a one-to-one onto mapping. The same reversibility requirements hold for stream ciphers and public-key ciphers like RSA. Although not much work has been carried out in the area of reversible implementations of cryptographic algorithms, this can be a very good area for future research. Similar considerations hold for various coding and decoding techniques used in communication, which are also inherently reversible in nature. Some examples of such coding/decoding are Manchester, Differential Manchester, Bipolar AMI, 4B/5B, 8B/10B, Hamming error correcting code, etc. All these techniques can potentially be implemented using reversible logic circuits. Specific case studies of some of the areas as mentioned will be reported, with synthesis results.

A modular approach for testable conservative reversible multiplexer circuit for nano-electronic confine application

Abstract: Quantum technology has an attractive application nowadays for its minimizing the energy dissipation, which is a prominent part of any system-level design. In this article, the significant module of a multiplexer, an extended to n:1 is framed with prominent application in the control unit of the processor. The proposed multiplexer modules are framed by the algorithm, which is extended perspective based. Further, quantum cost and gate count are less to ensure the efficient quantum computing framed. In addition, the QCA computing framework is an attempt to synthesize the optimal primitives in conservative reversible multiplexer in nano-electronic confine application. The developed lemmas is framed to prove the optimal parameters in the reversible circuit. Compared with existing state-of-art-works, the proposed modular multiplexer, the gate count, quantum cost and unit delay are optimal.

Programmable lowpower implementation of the HEVC Adaptive Loop Filter

Abstract: The Adaptive Loop Filter (ALF) is a subjective and objective image quality improving filter in the High Efficiency Video Coding standard (HEVC). The ALF has shown to be computationally complex and its complexity has been reduced during the HEVC development process. In the HEVC TestModel HM-7.0 ALF is a 9×7 cross + 3×3 square shaped filter. This paper presents a programmable application specific instruction processor for the ALF. The proposed processor processes 1920×1080p luminance frames at 30 frames per second, when operated at a clock frequency of 311MHz. Low power consumption and a low gate count make the proposed processor suitable for embedded devices. The processor program code is written in pure C-language, which allows versatile use of the circuit and updates to the filter functionality without modifying the processor design. To the authors' best knowledge this is the first programmable solution for ALF on embedded devices.