Topic
Gate count
About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.
Papers published on a yearly basis
Papers
More filters
•
31 Jan 1991
TL;DR: In this paper, a binary adder of the carry multiplex signal selection type is presented, where multiple levels of multiplexing between parallel carry paths are used to achieve improved adder performance as measured by adder fabrication area requirements and other performance criteria.
Abstract: A binary adder of the carry multiplex signal selection type wherein multiple levels of multiplexing between parallel carry paths is used to achieve improved adder performance as measured by adder fabrication area requirements and other performance criteria. The resulting adder employs a plurality of different adder stages of successively increasing complexity and achieves performance time that can be characterized as being of the order of Log2 (n), wherein n represents bit count, and as requiring a gate count that is of the order of n. Both internal arrangement of the adder stages and interconnection arrangements therefor are disclosed.
7 citations
••
TL;DR: In this paper, the digital implementation of the sawtooth map is analyzed to evaluate its suitability for pseudo-random binary numbers generation. But, the results show that values of design parameters that lead to adequate statistical features and to a relatively high period also allow for significantly reducing the complexity required in the implementation.
Abstract: In this paper, the sawtooth map digitally implemented is analysed to evaluate its suitability for pseudo-random binary numbers generation. Period and statistical properties of the sequences generated by the digital map are evaluated versus arithmetic precision, approximation strategy and characteristic parameter of the map.
In general, the digital implementation of the sawtooth map requires the use of a multiplier, which is quite expensive in terms of gate count. However, results show that values of design parameters that lead to adequate statistical features and to a relatively high period also allow for significantly reducing the complexity required in the implementation.
To better evaluate performance of the digital sawtooth map as a pseudo-random number generator, it is compared to a linear feedback shift register with the same number of flip-flops, which is well known for its output sequences with a long period, appealing statistical quality, and for a reduced gate count. Performance comparison and implementation on a programmable logic device show that the digital sawtooth map is suitable for pseudo-random number generation, also requiring a relatively small amount of hardware. Copyright © 2004 John Wiley & Sons, Ltd.
7 citations
••
TL;DR: A novel restructuring of the 2bit-SC (2b-SC) precomputation decoder architecture is carried out to reduce the latency by 20% while reducing the hardware complexity.
Abstract: Polar codes are one of the recently developed error correcting codes, and they are popular due to their capacity achieving nature. The architecture of the successive cancellation (SC) decoder algorithm is composed of a recursive processing element (PE). The PE comprises various blocks that include signed adder, subtractor, comparator, multiplexers, and few logic gates. Therefore, the latency of the PE is a primary concern. Hence, a high-speed architecture for implementing the SC decoding algorithm for polar codes is proposed. In the proposed work, a novel restructuring of the 2bit-SC (2b-SC) precomputation decoder architecture is carried out to reduce the latency by 20% while reducing the hardware complexity. Compared to the 2b-SC precomputation decoder, the proposed architecture also has 19% increased throughput for (1024, 512) polar codes with 45% reduction in the gate count.
7 citations
••
TL;DR: A new heuristic algorithm is proposed to optimize the power domain clustering in controlling-value-based (CV-based) power gating technology by considering both the switching activity of sleep signals and the overall numbers of sleep gates, and the sum of the product of p and N is optimized.
Abstract: In this paper, a new heuristic algorithm is proposed to optimize the power domain clustering in controlling-value-based (CV-based) power gating technology. In this algorithm, both the switching activity of sleep signals (p) and the overall numbers of sleep gates (gate count, N) are considered, and the sum of the product of p and N is optimized. The algorithm effectively exerts the total power reduction obtained from the CV-based power gating. Even when the maximum depth is kept to be the same, the proposed algorithm can still achieve power reduction approximately 10% more than that of the prior algorithms. Furthermore, detailed comparison between the proposed heuristic algorithm and other possible heuristic algorithms are also presented. HSPICE simulation results show that over 26% of total power reduction can be obtained by using the new heuristic algorithm. In addition, the effect of dynamic power reduction through the CV-based power gating method and the delay overhead caused by the switching of sleep transistors are also shown in this paper.
7 citations
••
01 Mar 1990TL;DR: A novel design for an M-user B-server arbiter for a multiple bus system that maintains fairness when it is used in a low-order interleaved memory system and is fair for a general-purpose multiprocessor system.
Abstract: A novel design for an M-user B-server arbiter for a multiple bus system is presented. The arbitration circuit maintains fairness when it is used in a low-order interleaved memory system. The arbiter is also fair for a general-purpose multiprocessor system where the memory modules are uniformly accessed by the processors. The arbitration time grows at a rate O(log/sub 2/ M), where M is the number of memory modules in a system. When a system has more than four memory modules, both the gate count and delay of the present design are less than those of previous designs. >
7 citations