Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

High-Throughput and Low-Power Architectures for Reed Solomon Decoder

Abstract: This paper presents a uniform comparison between various algorithms and architectures used for Reed Solomon (RS) decoder. For each design option, a detailed hardware analysis is provided, in terms of gate count, latency and critical path delay. A new low-power syndrome computation is proposed in the paper. Dual-line architecture of modified Berlekamp Massey algorithm was chosen for Ultra Wide-band (UWB) as an application example. The results obtained are very encouraging both in terms of silicon area and power. A detailed analysis of results is presented and they are also compared with other published industrial and academic designs. I. INTRODUCTION Reed Solomon (RS) codes have been widely used in a variety of communication systems. Continual demand for ever higher data rates and storage capacity makes it necessary to devise very high-speed implementations of RS decoders. A number of algorithms are available and this often makes it difficult to determine the best choice due to the number of variables and trade-offs available. For IEEE 802.15-03 standard proposal (commonly known as UWB) in particular, very high data rates for transmission are needed. Since the standard is also meant for portable devices, power consumption is of prime concern. There is no clear algorithm or architecture that can meet the low-power and high-throughput requirements of UWB. In this paper, a uniform comparison of various designs and architecture is presented. Dual-line architecture of BerleKamp Massey algorithm was implemented, with a lot of other optimisations to the conventional design. In the next section we present an introduction to RS codes and the decoder structure, followed by syndrome computation architecture. The design space is explored in the following section. We then present the results obtained for the archi- tecture chosen for UWB followed by some optimisations to the design. The results are then compared with existing architectures in the section on benchmarking followed by conclusions.

Block-Interlaced LDPC Decoders With Reduced Interconnect Complexity

Abstract: Two design techniques are proposed for high-throughput low-density parity-check (LDPC) decoders. A broadcasting technique mitigates routing congestion by reducing the total global wirelength. An interlacing technique increases the decoder throughput by processing two consecutive frames simultaneously. The brief discusses how these techniques can be used for both fully parallel and partially parallel LDPC decoders. For fully parallel decoders with code lengths in the range of a few thousand bits, the half-broadcasting technique reduces the total global wirelength by about 26% without any hardware overhead. The block interlacing scheme is applied to the design of two fully parallel decoders, increasing the throughput by 60% and 71% at the cost of 5.5% and 9.5% gate count overhead, respectively.

On the qubit routing problem

Abstract: We introduce a new architecture-agnostic methodology for mapping abstract quantum circuits to realistic quantum computing devices with restricted qubit connectivity, as implemented by Cambridge Quantum Computing's tket compiler. We present empirical results showing the effectiveness of this method in terms of reducing two-qubit gate depth and two-qubit gate count, compared to other implementations.

An efficient architecture for the AES mix columns operation

Abstract: In this paper, a compact architecture for the AES mix columns operation and its inverse is presented. The hardware implementation is compared with previous work done in this area. We show that our design has a lower gate count than other designs that implement both the forward and the inverse mix columns operation.

A near optimal deblocking filter for H.264 advanced video coding

Abstract: We propose a near optimal hardware architecture for deblocking filter in H.264/MPEG-4 AVC. We propose a novel filtering order and a data reuse strategy that result in significant saving in filtering time, local memory usage, and memory traffic. Every 16-16 macroblock requires 192 filtering operations. After a few initialization cycles, our 5-stage pipelined architecture is able to perform one filtering operation per cycle. Compared with some state-of-the-art designs, our architecture delivers the fastest level of performance while using much smaller gate count and memory. We have implemented and integrated the proposed deblocking filter into an H.264 main profile video decoder and verified it with an FPGA prototype.