Topic
Gate count
About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.
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16 May 2005
TL;DR: A method for estimating power consumption of digital CMOS VLSI chips is developed and an estimation tool is created and used to estimate the gate count from Verilog register transfer level (RTL) descriptions.
Abstract: A method for estimating power consumption of digital CMOS VLSI chips is developed. The method estimates the total power consumption of a chip by analyzing separately for different parts of the chip, which are logic circuit, on chip memory, interconnection, clock distribution, and off chip driving. This method makes it possible to estimate the power consumption of a digital CMOS VLSI chip based on gate count, memory size, and logic circuit. An estimation tool, which is implemented in C language, is created and used to estimate the gate count from Verilog register transfer level (RTL) descriptions
6 citations
15 May 2011
TL;DR: The revisiting prevention technique enables that the proposed ASIP can efficiently perform the fast search operations and supports not only the full search algorithm but also various fast search algorithms.
Abstract: This paper proposes Integer-pel Motion Estimation (IME) specific instructions and their hardware architecture for Application Specific Instruction-set Processor (ASIP). With parallel SAD Processing Elements (PEs) using pattern information, the proposed IME instruction supports not only the full search algorithm but also various fast search algorithms. Moreover, the revisiting prevention technique enables that the proposed ASIP can efficiently perform the fast search operations. The gate count is 43K gates for each Processing Element Group (PEG) which has 256 SAD PEs. The proposed ASIP with eight PEGs runs at 160MHz and can handle 1080p@30 frames in real-time.
6 citations
TL;DR: A new recursive recoding algorithm is proposed that shortens the critical path of the multiplier and reduces the hardware complexity of partial-product-generators as well and provides an optimal space/time partitioning of themultiplier architecture for any size N of the operands.
Abstract: This paper addresses the problem of multiplication with large operand sizes (N≥32). We propose a new recursive recoding algorithm that shortens the critical path of the multiplier and reduces the hardware complexity of partial-product-generators as well. The new recoding algorithm provides an optimal space/time partitioning of the multiplier architecture for any size N of the operands. As a result, the critical path is drastically reduced to 33√ N / 2 -- 3 with no area overhead in comparison to modified Booth algorithm that shows a critical path of N/2 in adder stages. For instance, only 7 adder stages are needed for a 64-bit two's complement multiplier. Confronted to reference algorithms for N=64, important gain ratios of 1.62, 1.71, 2.64 are obtained in terms of multiply-time, energy consumption per multiplyoperation, and total gate count, respectively.
6 citations
21 Mar 2016
TL;DR: A unified hardware architecture for 4×4, 8×8, 16×16 and 32×32 inverse 2D core transform IDCT in HEVC standard used only one block 1D transform and a transpose buffer based on FIFO memory blocs instead of the traditional register array in order to further reduce the memory resources.
Abstract: Most video coding standards use transform algorithms to reduce the size of data characterizing a video signal. The traditional transform matrices as in H.264 are limited to 4×4 and 8×8 sizes. However, the flexibility of coding structure presented in the next generation of video coding standard High Efficiency Video Coding standard HEVC allows the definition of various sizes of transform matrices which can vary from 4×4 to 32×32. This paper describes a unified hardware architecture for 4×4, 8×8, 16×16 and 32×32 inverse 2D core transform IDCT in HEVC standard. It used only one block 1D transform and a transpose buffer based on FIFO memory blocs instead of the traditional register array in order to further reduce the memory resources. The synthesis results under TSMC 180 nm CMOS technology show that the total gate count of the design is more than 30% improved compared to previous works. However, the operating frequency of the hardware design is about 130 MHz. This last can perform the decoding of 25 frames per second of Quad HD (3840×2160) resolution.
6 citations
03 Jun 2013
TL;DR: A low power multi-Lane Mobile Industry Processor Interface (MIPI) Camera Serial Interface 2 (CSI-2) receiver architecture which adopts an 8-Byte parallel CSI protocol layer for hardware implementations which reduces more than 37%~43% logic power consumption measured in chip.
Abstract: This paper proposes a low power multi-Lane Mobile Industry Processor Interface (MIPI) Camera Serial Interface 2 (CSI-2) receiver architecture which adopts an 8-Byte parallel CSI protocol layer for hardware implementations. The proposed scheme can work in environment with 4 data Lanes and 1 Gb/s per data Lane, i.e. with maximum data rate 4 Gb/s, at 62.5 MHz which increases logic operations from 8 ns (125 MHz) to 16 ns (62.5 MHz) without throughput degradation. Therefore, the supply voltage (1.2 V) can be reduced and the power consumption can also be reduced. The proposed architecture is implemented by 0.13 μm CMOS technology and the total gate count is 32.7 K. It not only reduces the operating clock rate but also reduces more than 37%~43% logic power consumption measured in chip.
6 citations