Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

Automatic accuracy management of quantum programs via (near-)symbolic resource estimation.

Abstract: When compiling programs for fault-tolerant quantum computers, approximation errors must be taken into account. We propose a methodology that tracks such errors automatically and solves the optimization problem of finding accuracy parameters that guarantee a specified overall accuracy while aiming to minimize a custom implementation cost. The core idea is to extract constraint and cost functions directly from the high-level description of the quantum program. Then, our custom compiler passes optimize these functions, turning them into (near-)symbolic expressions for (1) the total error and (2) the implementation cost (e.g., total gate count). All unspecified parameters of the quantum program will show up as variables in these expressions, including accuracy parameters. After solving the corresponding optimization problem, a circuit can be instantiated from the found solution. We develop two prototype implementations, one in C++ based on Clang/LLVM, and another using the Q# compiler infrastructure. We benchmark our prototypes on typical quantum computing programs, including the quantum Fourier transform, quantum phase estimation, and Shor's algorithm.

VLSI implementation of high throughput parallel pipeline median finder for IoT applications

Abstract: This paper proposes a high-throughput median finding architecture where the sorting of an incoming pixel is executed by a high-speed Compare and Select (CS) module. In this work, four clock pulses are required to populate the $$4\times 4$$ window as four pixels are read at a time from the incoming grey image. This median finding process is carried out by parallel and pipeline median a rchitecture. The proposed median finding process requires two read operations to take eight input pixels and generates four output pixels with a latency of seven clock cycles. The proposed architecture has been implemented on Xilinx Virtex–VII FPGA. The proposed architecture is synthesized using the SoC Encounter along with Faraday 90 nm standard cell library. The maximum operating frequency is 950.57 MHz, the total gate count is 4540, area is $$0.40543 \hbox { mm}^{2}$$ and the dissipated power is 0.92617 mW. The high-throughput, high-speed and low-power-dissipation nature of the proposed architecture make it suitable for computationally extensive Internet of Things (IoT) applications.

A Microarchitecture Implementation Framework for Online Learning with Temporal Neural Networks

Abstract: Temporal Neural Networks (TNNs) are spiking neural networks that use time as a resource to represent and process information, similar to the mammalian neocortex. In contrast to compute-intensive deep neural networks that employ separate training and inference phases, TNNs are capable of extremely efficient online incremental/continual learning and are excellent candidates for building edge-native sensory processing units. This work proposes a microarchitecture framework for implementing TNNs using standard CMOS. Gate-level implementations of three key building blocks are presented: 1) multi-synapse neurons, 2) multi-neuron columns, and 3) unsupervised and supervised online learning algorithms based on Spike Timing Dependent Plasticity (STDP). The proposed microarchitecture is embodied in a set of characteristic scaling equations for assessing the gate count, area, delay and power for any TNN design. Post-synthesis results (in 45nm CMOS) for the proposed designs are presented, and their online incremental learning capability is demonstrated.

Built-in Self-Test Implementation for an Analog-to-Digital Converter

Abstract: As integrated circuit fabrication techniques advance, a complex system can be integrated on a single chip: namely, a system-on-a-chip (SOC). A SOC consists of many intellectual property (IP) building blocks, including analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) which should provide certain built-in self-test (BIST) scheme to minimize the testing cost. Due to the analog nature of ADCs and DACs, digital BIST schemes are not applicable. This paper proposes a simple ADC BIST scheme based on a ramp test. The proposed BIST scheme is veried by simulation with a 6-bit pipelined ADC. Simulation results show that the proposed ADC BIST scheme can detect not only catastrophic faults but also some parametric faults. The total gate count of the proposed BIST circuit is about 150.

Design of optimal carry skip adder and carry skip bcd adder using reversible logic gates

Abstract: Reversible logic circuits have the ability to produ ce zero power dissipation which has found its importance in quantum computing, optical computing and low power digital circuits. The study presents improved and efficient reversible logic ci rcuits for carry skip adder and carry skip BCD adde r. The performance of the proposed architecture is bet ter than the existing works in terms of gate count, garbage outputs and constant inputs. This design fo rms the basis for different quantum ALU and embedded processors.