Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

Reducing Parallel Linear Feedback Shift Register Complexity Through Input Tap Modification

Abstract: BCH codes and cyclic redundancy check (CRC) are broadly used to ensure the reliability and integrity of data transmission. BCH encoders and CRC en/decoders are implemented by linear feedback shift registers (LFSRs). In prior LFSRs, the input is added to the most significant tap (MST), whose output is fed back and affects each of the other registers in the next clock cycle. The effects on the registers in a parallel design are translated to a pre-processing matrix multiplication, which may occupy the majority of the LFSR area. In this paper, we propose to add the input to the least significant tap (LST) and derive the corresponding parallel processing formula. Since the output of the LST is shifted to the MST before being fed back to the other taps, the corresponding pre-processing matrix is much simpler. Complexity reductions achievable by applying state-space transformations on LST-input LFSRs are evaluated and possible optimizations are discussed. For various CRCs considered, the proposed designs lead to 10–40% gate count reduction and significant power reduction compared to prior approaches with no or negligible penalty on the throughput.

16-channel two-parallel reed-solomon based forward error correction architecture for optical communications

Abstract: This paper presents a high-efficiency two-parallel Reed-Solomon (RS) decoder based on the compensated simplified reformulated inversionless Berlekamp-Massey (CS-RiBM) algorithm. To achieve high speed and low hardware complexity, the key equation solver (KES) block is designed by pipelining and folding processing. With TSMC 90nm process, the simulation results reveal that the 16-Channel proposed architecture can operate up to 625MHz and achieve a throughput rate of 156 Gbps with a total gate count of 269,000. The area of the proposed decoder is at least 35.6% fewer with the same technology, which meets the demands of next generation short-reach optical systems.

VLSI architecture designs for effective H.264/AVC variable block-size motion estimation

Abstract: In this paper, two hardware-oriented fast motion estimation algorithms and their implementations into a 2D systolic array for variable block size motion estimation architecture are presented. Two hardware oriented algorithms are proposed to increase the coding speed and reduce the computation complexity of the fast motion estimation (FME) algorithm. The results show that the proposed FME algorithm can speed up 71% coding time of the original standard with slightly PSNR loss and bit rate increase. Therefore, the hardware architecture designs for the proposed algorithms with considerations of both motion vector cost and the sum of absolute difference (SAD) distortion are implemented. The chip, which is realized in CMOS TSMC 0.13 mum 1P8M technology, can be operated at 200 MHz with gate count 191k including the memory modules.

Method and apparatus for encrypting data

Abstract: To improve data encryption and/or decryption, look-up tables in the field programmable gate array are used to store preselected values for the substitution box used in many encryption/decryption schemes. Utilizing look-up tables in such a manner reduces the overall gate count in the FPGA device resulting in quicker speeds, lower power consumption, and the ability to reconfigure the device for different encryption/decryption implementations.