Gate count

About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.

Parity Preserving Adder/Subtractor Using a Novel Reversible Gate

Abstract: Modern VLSI circuit design is governed by low power consumption requirements of ICs. Reversible logic has received great importance because of no information bit loss during computation which results in low power dissipation. Moreover, there is a need to convert the reversible circuits into fault tolerant reversible circuits to detect the occurrence of errors. Parity preserving property can be used for this. A new 5*5 parity preserving reversible gate is proposed in this paper, named as P2RG. The most significant aspect of this work is that it can work both as a full adder and a full subtract or by using one P2RG and Fred kin gate only. Proposed design is better in terms of gate count, garbage outputs, constant inputs and area than the existing similitudes. Thus, this paper provides the initial threshold to design more complex systems which will be able to execute more complicated operations using parity preserving reversible logic.

High Throughput Constant Envelope Pre-coder for Massive MIMO Systems

Abstract: This study describes a high throughput constant envelope (CE) pre-coder for Massive MIMO systems. A large number of antennas (M), in the order of 100s, serve a relatively small number of users (K) simultaneously. The stringent amplitude constraint (only phase changes) in the CE scheme is motivated by the use of highly power-efficient non-linear RF power amplifiers. We propose a scheme that computes the CE signals to be transmitted based on box-constrained regression (coordinatedescent),with an O(2MK) complexity per iteration per user symbol. A highly scalable systolic architecture is implemented, where M Processing Elements (PEs) perform the pre-coding for a system with up to K = 16 users. This systolic architecture results in a very high throughput of 500 Msamples/sec (at 500 MHz clock rate) with a gate count of 14 K per PE in 65 nm technology. (Less)

Variable length mixed radix MDC FFT/IFFT processor for MIMO-OFDM application

Abstract: This study presents a variable length multi-path delay commutator fast Fourier transform (FFT)/inverse FFT (IFFT) architecture for a multiple input multiple output orthogonal frequency division multiplexing system. It supports the FFT/ IFFT lengths of 512/256/128/64 samples to process each symbol carried by eight spatial streams and achieves a speed of 160 MHz to meet the IEEE 802.11ac timing requirements. A resource scheduling methodology to minimise the hardware complexity of the design is proposed and adopted in the architecture presented. A novel stagger word length strategy is also proposed and applied to achieve the better accuracy with lesser hardware. Here, the signal to quantisation noise ratio of 57.23 dB is obtained. The twiddle coefficient storage space is significantly compressed to achieve the coefficient generation with reduced hardware. The design is implemented using the TSMC-65 nm complementary metal oxide semiconductor technology with a supply voltage of 1 V at 160 MHz. The implementation results show that the architecture has a gate count of 3,48,013 with power consumption of 105.1 mW and area of 0.492 mm2. The hardware complexity and performance of the design are compared with earlier reported architectures. It is observed that the proposed design achieves better performance in terms of hardware complexity and normalised energy for the given specifications.

Composite field GF(((2 2 ) 2 ) 2 ) AES S-Box with direct computation in GF(2 4 ) inversion

Abstract: Composite field arithmetic (CFA) has been widely used in designing combinatorial logic circuits for the S-Box function in the Advanced Encryption Standard (AES) in order to mitigate the performance bottleneck in VLSI implementation. In this work, we first categorize all of the possible composite field AES S-box constructions into four main architectures based on their field representations and the chosen algebraic properties. Each category is then investigated thoroughly. Next, we show that by computing the F(24) inversion directly in the composite field F(((22)2)2), we can further reduce the total area gate count as well as the critical path gate count. The architecture that leads to the maximum reduction in both total area coverage and critical path gate count through the exploitation of direct computation in F(24) inversion is found and reported. Our best architecture has a total area gate count of 35 AND gates and 117 XOR gates and critical path gate count of 3 AND gates and 20 XOR gates.

An inversion/non-inversion dynamic optically reconfigurable gate array VLSI

Abstract: Up to now, an optically differential reconfigurable gate array taking a differential reconfiguration strategy and a dynamic optically reconfigurable gate array taking a photodiode memory architecture have been proposed. The differential reconfiguration strategy provides a higher reconfiguration frequency, with no increase in laser power, than other optically reconfigurable gate arrays, however the differential reconfiguration strategy can not achieve a high-gate-count VLSI because of the area occupied by the static configuration memory. On the other hand, the photodiode memory architecture can achieve a high-gate-count VLSI, but its configuration is slower than that of the optically differential reconfigurable gate array using equivalent laser power. So, this paper presents a novel inversion/non-inversion dynamic optically reconfigurable gate array VLSI that combines both architectures. It thereby achieves both advantages of rapid configuration and a high gate count. The experiments undertaken in this study clarify the effectiveness of the inversion/non-inversion optical configuration method.