Topic
Gate count
About: Gate count is a research topic. Over the lifetime, 1020 publications have been published within this topic receiving 13535 citations.
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25 Jun 2012
TL;DR: A protocol adapted to the requirements for on-chip data processing chains is introduced, inspired by the Remote Memory Access Protocol, but considerably simplified to limit the FPGA resource consumption for the implementation of a protocol handler, which needs to be instantiated in every single network node.
Abstract: State of the art radiation tolerant SRAM-based FPGAs with large gate count offer powerful processing capability among devices qualified for space applications. Due to changing mission requirements the processing in a space instrument needs to be adaptable. Modern SRAM-based FPGAs can be partially and dynamically reconfigured and thereby offer a method of adaptability. To provide a flexible communication architecture the partially reconfigurable modules were interconnected by a SoCWire Network-on-Chip. However to map an application on this network of exchangeable hardware processing nodes in the FPGA a communication protocol is required. This paper introduces a protocol adapted to the requirements for on-chip data processing chains. The protocol is inspired by the Remote Memory Access Protocol (RMAP), but considerably simplified to limit the FPGA resource consumption for the implementation of a protocol handler, which needs to be instantiated in every single network node. Despite offloading some of the processing into dedicated hardware cores implemented on a FPGA, a data processing unit still has to feature a controlling processor. To connect the Network-on-Chip and the processor, a controlling software complements the hardware protocol handler on the processor side.
5 citations
Patent•
29 Mar 2011TL;DR: In this article, the authors consider a display system configured to apply a panel gamma function that is a third-order polynomial function, as well as its substantial inverse, which is often easier to implement and yields lower gate count than current power law gamma functions.
Abstract: A cubic, or other polynomial, approximation to a panel's gamma function. Embodiments contemplate a display system configured to apply a panel gamma function that is a third-order polynomial function, as well as its substantial inverse. This third order function is often easier to implement, and yields lower gate count than current power law gamma functions.
5 citations
01 Jan 2003
TL;DR: By analyzing and improving high-radix Montgomery algorithm and FIPS method, a new algorithm that is suitable for signature card application is proposed and the former architecture of two multipliers computing in parallel so that the longest critical path of the whole design is greatly shortened.
Abstract: In this paper, a new implementation method to optimize a 1024-bit RSA crypto processor is presented. By analyzing and improving high-radix Montgomery algorithm and FIPS method we propose a new algorithm that is suitable for signature card application. A corresponding RAM management approach is introduced. We have improved the former architecture of two multipliers computing in parallel so that the longest critical path of the whole design is greatly shortened. Performance analysis is performed. As a case study, a 1024-bit RSA crypto processor is implemented. The average operating time to calculate 1024-bit modular exponentiation is 1.58M cycles. Based on TSMC 0.25mm standard cell library, the synthesis gate count is about 36K and the highest frequency is 66M. At this speed, 1024-bit message encryption needs only 27.7ms.
5 citations
29 Jul 2009
TL;DR: This paper presents the first demonstration of a 16-context DORGA architecture and presents experimental results: 530–833 ns reconfiguration times and 5-9.375 us retention times.
Abstract: Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits on a programmable device. Such dynamic reconfiguration necessitates two important features: fast reconfiguration and numerous contexts. However, because fast reconfiguration and numerous contexts share a tradeoff relation on current VLSIs, optically reconfigurable gate arrays (ORGAs) have been developed to resolve this dilemma.ORGAs can realize a large virtual gate count that is much larger than those of current VLSI chips by exploiting the large storage capacity of a holographic memory. Furthermore, ORGAs can realize fast reconfiguration through use of large bandwidth optical connections between a holographic memory and a programmable gate array VLSI. Among such developments, we have been developing dynamic optically reconfigurable gate arrays (DORGAs)that realize a high gate density VLSI using a photodiode memory architecture. This paper presents the first demonstration of a 16-context DORGA architecture. Furthermore, we present experimental results: 530–833 ns reconfiguration times and 5-9.375 us retention times.
5 citations
TL;DR: On-chip learning method is designed for standard benchmark XOR problem using back propagation based multilayer perceptron and is implemented in VIRTEX-E FPGA using VHDL.
5 citations