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Gate dielectric
About: Gate dielectric is a research topic. Over the lifetime, 25867 publications have been published within this topic receiving 468841 citations.
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TL;DR: Because monolayer MoS(2) has a direct bandgap, it can be used to construct interband tunnel FETs, which offer lower power consumption than classical transistors, and could also complement graphene in applications that require thin transparent semiconductors, such as optoelectronics and energy harvesting.
Abstract: Two-dimensional materials are attractive for use in next-generation nanoelectronic devices because, compared to one-dimensional materials, it is relatively easy to fabricate complex structures from them. The most widely studied two-dimensional material is graphene, both because of its rich physics and its high mobility. However, pristine graphene does not have a bandgap, a property that is essential for many applications, including transistors. Engineering a graphene bandgap increases fabrication complexity and either reduces mobilities to the level of strained silicon films or requires high voltages. Although single layers of MoS(2) have a large intrinsic bandgap of 1.8 eV (ref. 16), previously reported mobilities in the 0.5-3 cm(2) V(-1) s(-1) range are too low for practical devices. Here, we use a halfnium oxide gate dielectric to demonstrate a room-temperature single-layer MoS(2) mobility of at least 200 cm(2) V(-1) s(-1), similar to that of graphene nanoribbons, and demonstrate transistors with room-temperature current on/off ratios of 1 × 10(8) and ultralow standby power dissipation. Because monolayer MoS(2) has a direct bandgap, it can be used to construct interband tunnel FETs, which offer lower power consumption than classical transistors. Monolayer MoS(2) could also complement graphene in applications that require thin transparent semiconductors, such as optoelectronics and energy harvesting.
12,477 citations
TL;DR: In this paper, a review of the literature in the area of alternate gate dielectrics is given, based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success.
Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...
5,711 citations
TL;DR: In this article, the materials, charge-transport, and device physics of solution-processed organic field-effect transistors are reviewed, focusing in particular on the physics of the active semiconductor/dielectric interface.
Abstract: Field-effect transistors based on solution-processible organic semiconductors have experienced impressive improvements in both performance and reliability in recent years, and printing-based manufacturing processes for integrated transistor circuits are being developed to realize low-cost, large-area electronic products on flexible substrates. This article reviews the materials, charge-transport, and device physics of solution-processed organic field-effect transistors, focusing in particular on the physics of the active semiconductor/dielectric interface. Issues such as the relationship between microstructure and charge transport, the critical role of the gate dielectric, the influence of polaronic relaxation and disorder effects on charge transport, charge-injection mechanisms, and the current understanding of mechanisms for charge trapping are reviewed. Many interesting questions on how the molecular and electronic structures and the presence of defects at organic/organic heterointerfaces influence the device performance and stability remain to be explored.
1,651 citations
Book•
31 Mar 1991
TL;DR: In this paper, the authors present a set of techniques for defect detection in SOI materials, including the following: 2.1.1 Silicon-on-Zirconia (SOZ), 2.2.2 E-beam recrystallization, 2.3.3, 3.4.4, and 3.5.5 Other defect assessment techniques.
Abstract: 1 Introduction.- 2 SOI Materials.- 2.1 Introduction.- 2.2 Heteroepitaxial techniques.- 2.2.1 Silicon-on-Sapphire (SOS).- 2.2.2 Other heteroepitaxial SOI materials.- 2.2.2.1 Silicon-on-Zirconia (SOZ).- 2.2.2.2 Silicon-on-Spinel.- 2.2.2.3 Silicon on Calcium Fluoride.- 2.3 Dielectric Isolation (DI).- 2.4 Polysilicon melting and recrystallization.- 2.4.1 Laser recrystallization.- 2.4.2 E-beam recrystallization.- 2.4.3 Zone-melting recrystallization.- 2.5 Homoepitaxial techniques.- 2.5.1 Epitaxial lateral overgrowth.- 2.5.2 Lateral solid-phase epitaxy.- 2.6 FIPOS.- 2.7 Ion beam synthesis of a buried insulator.- 2.7.1 Separation by implanted oxygen (SIMOX).- 2.7.1.1 "Standard"SIMOX.- 2.7.1.2 Low-dose SIMOX.- 2.7.1.3 ITOX.- 2.7.1.4 SMOXMLD.- 2.7.1.5 Related techniques.- 2.7.1.6 Material quality.- 2.7.2 Separation by implanted nitrogen (SIMNI).- 2.7.3 Separation by implanted oxygen and nitrogen (SIMON).- 2.7.4 Separation by implanted Carbon.- 2.8 Wafer Bonding and Etch Back (BESOI).- 2.8.1 Hydrophilic wafer bonding.- 2.8.2 Etch back.- 2.9 Layer transfer techniques.- 2.9.1 Smart-Cut(R).- 2.9.1.1 Hydrogen / rare gas implantation.- 2.9.1.2 Bonding to a stiffener.- 2.9.1.3 Annealing.- 2.9.1.4 Splitting.- 2.9.1.5 Further developments.- 2.9.2 Eltran(R).- 2.9.2.1 Porous silicon formation.- 2.9.2.2 The original Eltran(R) process.- 2.9.2.3 Second-generation Eltran(R) process.- 2.9.3 Transferred layer material quality.- 2.10 Strained silicon on insulator (SSOI).- 2.11 Silicon on diamond.- 2.12 Silicon-on-nothing (SON).- 3 SOI Materials Characterization.- 3.1 Introduction.- 3.2 Film thickness measurement.- 3.2.1 Spectroscopic reflectometry.- 3.2.2 Spectroscopic ellipsometry.- 3.2.3 Electrical thickness measurement.- 3.3 Crystal quality.- 3.3.1 Crystal orientation.- 3.3.2 Degree of crystallinity.- 3.3.3 Defects in the silicon film.- 3.3.3.1 Most common defects.- 3.3.3.2 Chemical decoration of defects.- 3.3.3.3 Detection of defects by light scattering.- 3.3.3.4 Other defect assessment techniques.- 3.3.3.5 Stress in the silicon film.- 3.3.4 Defects in the buried oxide.- 3.3.5 Bond quality and bonding energy.- 3.4 Carrier lifetime.- 3.4.1 Surface Photovoltage.- 3.4.2 Photoluminescence.- 3.4.3 Measurements on MOS transistors.- 3.4.3.1 Accumulation-mode transistor.- 3.4.3.2 Inversion-mode transistor.- 3.4.3.3 Bipolar effect.- 3.5 Silicon/Insulator interfaces.- 3.5.1 Capacitance measurements.- 3.5.2 Charge pumping.- 3.5.3 ?-MOSFET.- 4 SOI CMOS Technology.- 4.1 SOI CMOS processing.- 4.1.1 Fabrication yield and fabrication cost.- 4.2 Field isolation.- 4.2.1 LOCOS.- 4.2.2 Mesa isolation.- 4.2.3 Shallow trench isolation.- 4.2.4 Narrow-channel effects.- 4.3 Channel doping profile.- 4.4 Source and drain engineering.- 4.4.1 Silicide source and drain.- 4.4.2 Elevated source and drain.- 4.4.3 Tungsten clad.- 4.4.4 Schottky source and drain.- 4.5 Gate stack.- 4.5.1 Gate material.- 4.5.2 Gate dielectric.- 4.5.3 Gate etch.- 4.6 SOI MOSFET layout.- 4.6.1 Body contact.- 4.7 SOI-bulk CMOS design comparison.- 4.8 ESD protection.- 5 The SOI MOSFET.- 5.1 Capacitances.- 5.1.1 Source and drain capacitance.- 5.1.2 Gate capacitance.- 5.2 Fully and partially depleted devices.- 5.3 Threshold voltage.- 5.3.1 Body effect.- 5.3.2 Short-channel effects.- 5.4 Current-voltage characteristics.- 5.4.1 Lim & Fossum model.- 5.4.2 C?-continuous model.- 5.5 Transconductance.- 5.5.1 gm/ID ratio.- 5.5.2 Mobility.- 5.6 Basic parameter extraction.- 5.6.1 Threshold voltage and mobility.- 5.6.2 Source and drain resistance.- 5.7 Subthreshold slope.- 5.8 Ultra-thin SOI MOSFETs.- 5.8.1 Threshold voltage.- 5.8.2 Mobility.- 5.9 Impact ionization and high-field effects.- 5.9.1 Kink effect.- 5.9.2 Hot-carrier degradation.- 5.10 Floating-body and parasitic BJT effects.- 5.10.1 Anomalous subthreshold slope.- 5.10.2 Reduced drain breakdown voltage.- 5.10.3 Other floating-body effects.- 5.11 Self heating.- 5.12 Accumulation-mode MOSFET.- 5.12.1 I-V characteristics.- 5.12.2 Subthreshold slope.- 5.13 Unified body-effect representation.- 5.14 RF MOSFETs.- 5.15 CAD models for SOI MOSFETs.- 6 Other SOI Devices.- 6.1 Multiple-gate SOI MOSFETs.- 6.1.1 Multiple-gate SOI MOSFET structures.- 6.1.1.1 Double-gate SOI MOSFETs.- 6.1.1.2 Triple-gate SOI MOSFETs.- 6.1.1.3 Surrounding-gate SOI MOSFETs.- 6.1.1.4 Triple-plus gate SOI MOSFETs..- 6.1.2 Device characteristics.- 6.1.2.1 Current drive.- 6.1.2.2 Short-channel effects.- 6.1.2.3 Threshold voltage.- 6.1.2.4 Volume inversion.- 6.1.2.5 Mobility.- 6.2 MTCMOS/DTMOS.- 6.3 High-voltage devices.- 6.3.1 VDMOS and LDMOS.- 6.3.2 Other high-voltage devices.- 6.4 Junction Field-Effect Transistor.- 6.5 Lubistor.- 6.6 Bipolar junction transistors.- 6.7 Photodiodes.- 6.8 G4 FET.- 6.9 Quantum-effect devices.- 7 The SOI MOSFET in a Harsh Environment.- 7.1 Ionizing radiations.- 7.1.1 Single-event phenomena.- 7.1.2 Total dose effects.- 7.1.3 Dose-rate effects.- 7.2 High-temperature operation.- 7.2.1 Leakage current.- 7.2.2 Threshold voltage.- 7.2.3 Output conductance.- 7.2.4 Subthreshold slope.- 8 SOI Circuits.- 8.1 Introduction.- 8.2 Mainstream CMOS applications.- 8.2.1 Digital circuits.- 8.2.2 Low-voltage, low-power digital circuits.- 8.2.3 Memory circuits.- 8.2.3.1 Non volatile memory devices.- 8.2.3.2 Capacitorless DRAM.- 8.2.4 Analog circuits.- 8.2.5 Mixed-mode circuits.- 8.3 Niche applications.- 8.3.1 High-temperature circuits.- 8.3.2 Radiation-hardened circuits.- 8.3.3 Smart-power circuits.- 8.4 Three-dimensional integration.
1,627 citations
TL;DR: The encapsulation makes graphene practically insusceptible to the ambient atmosphere and, simultaneously, allows the use of boron nitride as an ultrathin top gate dielectric.
Abstract: Devices made from graphene encapsulated in hexagonal boron-nitride exhibit pronounced negative bend resistance and an anomalous Hall effect, which are a direct consequence of room-temperature ballistic transport at a micrometer scale for a wide range of carrier concentrations. The encapsulation makes graphene practically insusceptible to the ambient atmosphere and, simultaneously, allows the use of boron nitride as an ultrathin top gate dielectric.
1,568 citations