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Gate dielectric
About: Gate dielectric is a research topic. Over the lifetime, 25867 publications have been published within this topic receiving 468841 citations.
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TL;DR: In this article, a thorough investigation of trapped-hole induced gate oxide deterioration and simulation results of time-dependent dielectric breakdown (TDDB) of thin (7-25)nm) silicon dioxide (SiO2) films thermally grown on (0 0 0 1) silicon (Si) face of n-type 6H-silicon carbide (n-6H-SiC).
Abstract: We present for the first time a thorough investigation of trapped-hole induced gate oxide deterioration and simulation results of time-dependent dielectric breakdown (TDDB) of thin (7–25 nm) silicon dioxide (SiO2) films thermally grown on (0 0 0 1) silicon (Si) face of n-type 6H-silicon carbide (n-6H-SiC). Gate oxide reliability was studied during both constant voltage and current stress with positive bias on the degenerately doped n-type poly-crystalline silicon (n+-polySi) gate at a wide range of temperatures between 27 and 225 °C. The gate leakage current was identified as the Poole-Frenkel (PF) emission of electrons trapped at an energy 0.92 eV below the SiO2 conduction band. Holes were generated in the n+-polySi anode material as well as in the oxide bulk via band-to-band ionization depending on the film thickness tox and the energy of the hot-electrons (emitted via PF mechanism) during their transport through oxide films at oxide electric fields Eox ranging from 5 to 10 MV/cm. Our simulated time-to-...
10 citations
TL;DR: In this paper, the performance of double-gate OTFTs with different ammonium dichromate (ADC) concentrations and exposure times were obtained from 6.73 to 10.5 and 6.37 to 4.87 A/cm 2 ) respectively.
10 citations
TL;DR: In this paper, the authors investigate the passivation of p-Ge(001) using molecular H"2S. The modification of the semiconductor surface is monitored in situ by RHEED and the interface is characterized by XPS analyses.
10 citations
Patent•
03 Jun 2002TL;DR: In this article, a semiconductor fabrication method of forming a pair of transistor gates of opposite conductivity type by partially forming first and second gate stacks comprising an insulation layer, a conductive layer and polysilicon layer was proposed.
Abstract: A semiconductor fabrication method of forming a pair of transistor gates of opposite conductivity type by partially forming first and second gate stacks comprising an insulation layer, a conductive layer and polysilicon layer for the pair of transistor by removing a portion of the polysilicon layer The polysilicon layer includes a dominant region of first-type conductive dopants and a dominant region of second-type conductive dopants A first-type conductive transistor gate is formed by, completing the formation of the first gate stack and a second-type conductive transistor gate is formed by completing the formation of the second gate stack separately from the formation of the first-type transistor gate
10 citations
Patent•
26 Jul 1990TL;DR: In this article, a MOS structure is formed on a silicon semiconductor substrate surface using a first gate electrode film made of polysilicon, an element isolation groove reaching the inside of the silicon substrate is formed, and an insulating film is filled in the groove.
Abstract: A MOS structure is formed on a silicon semiconductor substrate surface using a first gate electrode film made of polysilicon, an element isolation groove reaching the inside of the silicon semiconductor substrate is formed, and an insulating film is filled in the groove. In addition, a second gate electrode film made of a refractory metal such as molybdenum silicide is formed to be connected to the first gate electrode film, and the first and second gate electrode films are simultaneously removed to form a MOS gate electrode and a wiring layer.
10 citations