Gate driver

Abstract: We designed, prototyped, and evaluated LCD integrated with a gate driver and a source driver using amorphous In-Ga-Zn-Oxide TFTs having bottom-gate bottom-contact structure, thereby obtaining TFTs with superior characteristics Then, we prototyped the world's first 4-inch QVGA LCD and integrated the gate driver and source driver on the display panel

Abstract: This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.

Abstract: In this paper, a new topology of cascaded multilevel inverter using a reduced number of switches, insulated gate driver circuits and voltage standing on switches is proposed. The proposed topology results in reduction of installation area and cost and has simplicity of control system. This structure consists of series connected sub-multilevel inverters blocks. Three algorithms for determination of magnitudes of dc voltage sources have been presented, too. Validity of the analysis has been proved by simulation and experimental results.

Abstract: In this paper, a new topology for cascaded multilevel converter based on submultilevel converter units and full-bridge converters is proposed. The proposed topology significantly reduces the number of dc voltage sources, switches, IGBTs, and power diodes as the number of output voltage levels increases. Also, an algorithm to determine dc voltage sources magnitudes is proposed. To synthesize maximum levels at the output voltage, the proposed topology is optimized for various objectives, such as the minimization of the number of switches, gate driver circuits and capacitors, and blocking voltage on switches. The analytical analyses of the power losses of the proposed converter are also presented. The operation and performance of the proposed multilevel converter have been evaluated with the experimental results of a single-phase 125-level prototype converter.

Abstract: An apparatus and method for driving a liquid crystal display device are disclosed. The apparatus includes a liquid crystal panel with pixels defined by data and gate lines. A gate driver provides different gate pulses to the odd-column pixels than to the even-column pixels. The gate pulses have different voltages and/or widths. Data drivers provide data voltages having a positive or negative polarity to the data lines. A timing controller controls the gate and data drivers and supplies gate clock pulses that have different voltages and/or widths to the gate driver.