Showing papers on "Gate driver published in 1975"

Solid state fail-safe logic system

Abstract: A solid state fail-safe logic system is disclosed including AND and OR gates which are designed as an evolutionary replacement for signal control functions previously performed by vital front and back contacts of vital relays and power check logic. The AND gate is basic and accepts an a.c. and a d.c. input. The a.c. input circuit includes a light emitting diode optically coupled to a light receiving active circuit means. Leakage currents cannot falsely activate the gate since the light emitting diode is poled to be reverse biased by the supply voltage. The d.c. input is protected from leakage currents by proper connections so that any leakage current is of the wrong polarity to produce an output. The d.c. input provides forward bias for light responsive active circuit means. The AND gate is divided into an input module including the light emitting diode and an output module inciuding the light responsive active circuit means. An OR gate is provided by using an AND gate output module and one AND gate input module for each OR gate input. More complex logic functions can be implemented and other devices, such as relays, simulated, by combining the AND or OR gates with other circuits.

Signal amplifier circuit using a pair of complementary junction field effect transistors

Abstract: A signal amplifier circuit includes at least one pair of complementary junction field effect transistors serially connected in a source-to-source relationship between first and second power supply source terminals. In order to apply a reverse bias between the gate and source in each of the paired transistors, the gate bias potential of one of the paired transistors can be selected between a potential on the first power supply terminal and a potential of the commonly connected sources of the transistor pair, and the gate bias potential of the other transistor be selected between a potential at the second power supply terminal and the potential of the commonly connected sources of the transistor pair. According to this invention, direct coupling can be easily effected between amplifier stages using a common power supply source.

Method and system of driving power field effect transistor

Abstract: A method and a system of obtaining a large power with the use of a junction field effect transistor by extending the working range to improve the utilization rate of the power source voltage. The range for the gate voltage is set up to some predetermined forward voltage at which the gate and the source will be subjected to a forward biasing. The source-to-drain internal resistance is reduced by this forward gate voltage, but no gate current is allowed to flow probably due to the existence of a non-linear element between the gate and the source.

Complementary field effect transistor linear amplifier

Abstract: A linear voltage amplifier includes an input stage which has a P channel MOSFET load device and an N channel input device. The complementary amplifier also includes a feedback circuit which includes a low pass filter coupled between the output stage and the gate electrode of the P channel load device. The P type tub region in which the N channel input MOSFET is located is biased by an adjustable bias circuit to control threshold voltage of the input MOSFET and thereby control the DC level of the output of the complementary amplifier. In one embodiment the biasing circuit includes a P channel MOSFET coupled in series with a diode connected N channel MOSFET between two voltage supply conductors, the gate of the P channel MOSFET being connected to the gate of the P channel MOSFET load device of the input stage. The junction between the P channel MOSFET and the diode connected N channel MOSFET is coupled to one terminal of a high value resistor, the other end of which is connected to the input conductor which is connected to the gate of the N channel input MOSFET.

A high power MOSFET with a vertical drain electrode and meshed gate structure

Abstract: A power MOSFET is developed which exhibits 20A current, 3000mΩ transconductance and 85V breakdown voltage in a 5×5mm2chip. The features of the device structure are a vertical drain electrode which enables to use most of the surface area for the source electrode and a mesh gate structure which makes able to increase the channel width per unit area, thereby drain current of the device can be increased. The P-channel device with an offset gate structure was fabricated from an N on P+epitaxial wafer by using the polysilicon gate and the ion implantation processes. The device can be operated stably at ambient temperatures up to 180°C.