Showing papers on "Gate driver published in 1977"

Circuit for increasing the output current in MOS transistors

Abstract: In order to increase the output current of an MOS transistor, its gate is provided with a switched capacitor drive. A tri-state inverter is used to drive the output transistor gate from an input source. A pair of delay elements are cascaded to drive one input of a NOR gate, the other input of which is fed an undelayed signal. The NOR gate is used to switch a capacitor that is also coupled to the output transistor gate. The juncture between the delays is coupled to the control electrode of the tri-state inverter. During the first delay interval, the capacitor and the output transistor gate electrode are charged. Then after the second delay interval, which is shorter than the first, the capacitor is discharged into the output transistor gate electrode which is thereby driven substantially in excess of the conventional drive level.

Sensitive high speed solid state preamp

Abstract: A preamp for coupling to an avalanche photodiode (APD) of an optical receiver has an input stage including a dual gate field effect transistor (FET) and a single gate FET coupled in a cascade arrangement. The dual gate FET has its first gate coupled to the output of the APD, its second gate and source grounded, and its drain driving the gate of the single gate FET in a cascade arrangement. The source of the single gate FET is level-shifted and coupled by means of a feedback resistor to the first gate of the dual gate FET to provide a negative feedback. The output stage is a third FET with its gate coupled through a blocking capacitor to the source of the single gate FET in the input stage and with its drain providing the output of the preamp. In a preferred embodiment, the FETs used are GaAs FETs (GAASFETs).

Selective gate circuit

Abstract: PURPOSE:To obtain a selective gate circuit which increases the integration degree by using the transmission gate composed of C-MOS without impairing the function as a selective gate.

Fatigue phenomena of FTMIS memory transistors

Abstract: Two operation modes of long endurance and their fatigue properties are described for a nonvolatile charge storage memory device which employs a floating silicon gate tunnel injection MIS (FTMIS) structure. The device is composed of an n-channel metal gate field effect transistor with a floating gate over tunnelable (20-35 A) SiO 2 . The floating gate consists of highly resistive polycrystalline Si grains. Gate oxidation isolates each poly-Si grain, resulting in a structure of islands. This improves retention characteristics. The primary feature of these devices is that no fatigue phenomena are observed for 2 × 1012cycles continuous write-erase operation in the conventional operation mode. In addition, it is possible both to write and erase in the other operation mode with only positive pulses to the gate electrode. Furthermore, stored data is retained more than one year without any external power supply. Therefore the device is an excellent candidate for nonvolatile RAM applications as a semiconductor memory device.

Amplifier stage for the current supply of I2 L circuits

Abstract: An amplifier stage is provided for supplying differing currents to integrated injection logic I2 L circuits. The amplifier stage has a current hogging injection logic input CHIL gate, at least one further gate, and a CHIL output gate. Each of the gates has an injecting emitter, an output and an input. First I2 L circuits connected to a first injector path connect with the input of the CHIL input gate. Second I2 L circuits having a second injector path connect with an output of the CHIL output gate. The gate provided between the input and output CHIL gates is provided as a single I2 L gate, dual I2 L gates, or the combination of an I2 L gate and a CHIL gate.

Semiconductor controlling rectifying device

Abstract: PURPOSE:To reduce the power consumed by gate signals and reduce the size of gate driver circuits by disposing another gate electrode of a smaller counter length in opposition to one end of cathode electrode