Showing papers on "Gate driver published in 1980"

Inverter circuits using insulated gate field effect transistors

Abstract: An inverter circuit comprises a pair of N- and P-channel insulated gate field effect transistors coupled in series. One of the transistors is used as a load transistor and the other is used as a drive transistor. A diode is connected between the source and gate electrodes of the load transistor in order to hold the gate voltage of the load transistor. A resistor and a capacitor (having a larger capcitance than the gate capacitance of the load transistor) is connected to the gate electrode of the load transistor. In operation, a high voltage is applied to the source electrode of the load transistor. A low-voltage pulse, having a period shorter than the RC time constant of the resistor and capacitor, is applied through the capacitor to the gate electrode of the load transistor. The gate electrode of the drive transistor is supplied with a low-voltage input signal (having a phase which is the same as and not longer than the period of the pulse applied to the capacitor). An input pulse signal may be used as the low-voltage pulse which is applied to the capacitor.

Electronic gate control

Abstract: A logic control and safety circuit for an electrically actuated gate, or the like. Upon command, a counter directs pulses from a free running oscillator of selective frequency to timer and motor control circuitry, effecting sequential gate operations. The normal gate sequence includes open, pause, and close cycles. Electro-mechanical and electrical safety features are included should the gate encounter an obstruction during either the open or the close cycles, or fail to complete a cycle for any reason. Automatic reset circuitry advances the gate through a "close" cycle following a power failure.

Non-volatile semiconductor memory circuits

Abstract: Memory circuits having a floating gate transistor as a non-volatile storage element are constructed with a shunt transistor across the floating-gate transistor which in the event of a short circuit between the floating gate and the transistor substrate causes the memory to go into a predetermined fail-safe condition. The circuits are cross-coupled flip-flops with a driver and a complementary driver or load connected in series in each of the circuits, one driver or complementary driver or load being a floating gate transistor such as a FATMOS. Short circuiting of the floating gate to the control gate of the floating-gate transistor gives the same fail-safe condition.

Josephson logic gate device

Abstract: A Josephson logic gate device comprises a closed loop of four Josephson junctions, a gate line and a ground line connected to the closed loop at symmetrically opposite points, and a control line connected to the closed loop at the intermediate joint between the gate line and ground line This logic gate produces a switching function in which the gate current fed to the gate line is steered from the gate to the load by the transition between the zero-voltage state and the voltage state of the device when a control current is supplied into the control line

Self-switching bidirectional digital line drivers

Abstract: To provide reduced vulnerability to glitches, a self switching bidirectional digital line driver comprises two identical circuits (10; 20), coupled in opposite senses between interface nodes (11, 21) and comprising a receiver (12; 22), a NOR gate (13; 23) and a transmitter (20; 15) and a transmitter connected in series. The output (14; 24) of each gate supplies an input to the other gate directly and via a latch (16; 26), resettable by the output of the opposing receiver. Each transmitter has one relaxed mode preferably provided by an open collector transistor and the logic is such that from a rest state corresponding to both transmitters being in the relaxed mode, the switching of one gate locks the other gate into the relaxed mode.

High voltage driver amplifier apparatus

Abstract: A high voltage driver amplifier apparatus utilizing two high-voltage, current switches which are controlled by gated logic circuits, to connect a capacitive load to either a positive or negative high voltage power source.

Complementary amplifier circuit

Abstract: A complementary amplifier circuit includes a p-channel MISFET and an n-channel MIS connected in series. The gate of the p-channel FET transistor is D.C. biased by a high impedance resistor connected between the gate and drain electrodes, and the gate of the n-channel FET is D.C. biased by a current mirror circuit formed by another n-channel FET. This complementary amplifier circuit has the advantages that the operational lower limit voltage thereof is equal to the threshold voltage of one of the MOSFETs and that stabilized operation of the amplifier is easily obtained.

Gate driver for gate turnnoff thyristor

Abstract: PURPOSE:To shorten extremely the time until a protection circuit is operated by detecting the abnormality of a turn-off power circuit from the increase rate of the rise of negative gate current and then by putting aprotecting power circuit to work. CONSTITUTION:Between the gate and cathode, gate driver unit 22 and protecting power circuit 23 are connected in parallel and to main unit 22, gate turn-off power circuit 26 of electronic switch 24 and direct-current power supply 25 connected in series and gate turn-off power circuit 29 of series-connected direct-current power supply 27 and electronic switch 28 in parallel to circuit 26 are both connected. Once the output of power supply 27 lowers, the increase rate of a negative gate current falls to decrease a voltage across inductance 34 down to less than a reference value, no output is generated by comparator 35 and AND gate 37 becomes open at a lagging point in time, so that the output of inverter 39 will be ''0''. At the same time, both the terminals of capacitor 23 charged higher than the prescribed voltage of power supply 27 are connected between the gate and cathode of GTO3. As a result, GTO3 turns OFF without breaking down by heating.

Transfer control system of bubble memory

Abstract: PURPOSE:To shorten access time, etc., without deteriorating the margin of operation by controlling the revolving speed of a revolving magnetic field for magnetic bubble transfer in accordance with whether gate operation should be put in effect or not. CONSTITUTION:According to control signal S1 from timing control circuit 14, a composite magnetic field is formed by X and Y coils 11 and 12 of memory chip 9 through coil driver circuit 13 to transfer magnetic bubbles on a loop in accordance with the revolving speed of the revolving magnetic field in proportion to the frequency of signal S1. When those bubbles reach a gate and gate operation is performed through gate driver circuit 15, etc., by control signal S4 from circuit 14, signal S1 from circuit 14 lowers in frequency and the transfer speed of bubbles lowers and then increases, so that the gate operation with the margin of operation small will stably be performed. As for sense circuit 16, the margin of operation do not lower similarly and access time and access cycle time are shortened because bubbles are transferred at a high speed in a period having no relation to the margin of operation.