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Showing papers on "Gate driver published in 1981"


Patent
07 Apr 1981
TL;DR: In this paper, an ultrasonic flowmeter including a pair of alternately-excited upstream and downstream transducers, an acoustic pulse emitted by one transducer and propagated through the fluid being received by the other, is measured to determine the flow rate of the fluid.
Abstract: An ultrasonic flowmeter including a pair of alternately-excited upstream and downstream transducers, an acoustic pulse emitted by one transducer and propagated through the fluid being received by the other. The time delay difference between the upstream and downstream transit times is measured to determine the flow rate of the fluid. A single pulse power generating device is employed to excite both transducers, the device being coupled to the transducers through respective gates, each activated by an associated gate driver. Also included are logic means to periodically activate the device to produce power pulses and to alternately activate the gate drivers to cause the pulses to pass through alternate gates to excite one transducer and then the other.

11 citations


Journal ArticleDOI
TL;DR: In this paper, a new Si MOSFET was proposed, featuring an insulated gate structure, channel doping, and finite spacing between gate and source and between gate between drain and drain, and two-dimensional numerical analysis showed that punchthrough is suppressed and that minimum gate length, limited bypunchthrough or V T shift, is extended into the submicrometer range.
Abstract: A new device structure is proposed for Si MOSFET, featuring an insulated gate structure, channel doping, and finite spacing between gate and source and between gate and drain. Two-dimensional numerical analysis shows that punchthrough is suppressed and that minimum gate length, limited bypunchthrough or V T shift, is extended into the submicrometer range.

10 citations


Journal ArticleDOI
K. Yamaguchi1, S. Takahashi
TL;DR: In this paper, a submicron gate MOSFET with a new device structure is presented, which features gate separation between the source and gate and between the gate and drain.
Abstract: Submicron gate MOSFET's with a new device structure are presented. The device features gate separation between the source and gate and between the gate and drain. The minimum gate length limited by V TH lowering is extended into the submicron range. Experimental results showed pentode-like current-voltage characteristics without punchthtough, even in the submicron range. Experimental results of inverter circuits and theoretical analysis predict high-speed operation in the subnanosecond region.

8 citations


Patent
23 Jun 1981
TL;DR: In this article, a gate driving circuit for a depletion type, static induction transistor, including a capacitor coupled between the emitters of complementary-connected NPN and PNP transistors and the SIT gate, high value resistor parallel-connected to a series connection of a diode and a resistor between the sIT gate and a negative gate voltage source is described.
Abstract: The disclosure relates to a gate driving circuit for a depletion type, static induction transistor, including a capacitor coupled between the emitters of complementary-connected NPN and PNP transistors and the SIT gate, high value resistor parallel-connected to a series connection of a diode and a resistor between the SIT gate, and a negative gate voltage source

5 citations


Patent
James E. Morris1
11 Dec 1981
TL;DR: In this article, a gate-to-source voltage of an FET at a region of gate current below some maximum value is kept below the maximum value of the FET voltage.
Abstract: Disclosed is a circuit for biasing FETs which limits unwanted gate current. A first resistor (R 8 ) is coupled in series with the gate and the output (14) of a differential amplifier (12). Means such as a second resistor (R 9 ) and a Zener diode (D 2 ) are coupled to the first resistor and one input of the differential amplifier. Means such as a third resistor (R 3 ) is also coupled to one input of the amplifier. When excessive gate current appears, the voltage across the first resistor is such as to cause sufficient current flow through the diode and second and third resistors to unbalance the amplifier. This keeps the gate-to-source voltage of the FET at a region of gate current below some maximum value.

3 citations


Patent
08 Jun 1981
TL;DR: In this paper, a gate protection circuit of an MOSFET is proposed to obstruct dielectric breakdown of a gate against a negative pulse surge voltage by a method wherein a diffusion resistor which keeps a gate retained at a high potential side of a power source or at a low potential side is used.
Abstract: PURPOSE:To surely obstruct a dielectric breakdown of a gate against a negative pulse surge voltage by a method wherein a diffusion resistor which keeps a gate retained at a high potential side of a power source or at a low potential side is used in a gate protection circuit of an MOSFET. CONSTITUTION:A terminal 14 of a diffusion resistor providing a gate structure is connected to an input terminal and the other terminal 15 is connected to a gate of an MOSFET1, respectively. A gate 16 is retained at a low potential side of a power source. During an ordinary time, a P area directly under the gate 16 is in a continuity state, as a result, an input signal is transferred to the gate of the MOSFET1 through a certain resisting component, however, when a negative surge voltage is applied, a depletion layer spreads from the P area directly under the gate 16. And the space between the P area and a substrate 11 is biased inversely by a negative surge voltage and a depletion layer spreads in the same way. The space between terminals 14 and 15 is interrupted by this depletion layer, thus, no surge voltage being transferred to the gate of the MOSFET1.

1 citations


Patent
29 Jul 1981
TL;DR: In this paper, a temperature-stabilised circuit arrangement for fault-tolerant logic modules is proposed, where the input signals are supplied to separate input transformers and are rectified in their secondary circuits by means of inserted rectifier arrangements.
Abstract: Circuit arrangement for a fault-tolerant logic module. The circuit arrangement provides: a) that the input signals are supplied to separate input transformers and are rectified in their secondary circuits by means of inserted rectifier arrangements, b) that the rectified input signals form the individual control potentials for a subsequent transistor blocking oscillator circuit with feedback transformer, c) that the pulse voltage of the blocking oscillator is supplied to the output via an amplifier stage inserted in the secondary circuit of the feedback transformer. For generating a programmed drop-out-delayed signal, a temperature-stabilised circuit arrangement is achieved by the fact that a fail-safe AND gate modified by a clock generator (G) at one input and a fail-safe OR gate are connected to one another in such a manner that the input of the AND gate, to which the input signal is applied, is connected to the input of the OR gate, that the output (A) of the OR gate is fed back to the input of the AND gate to which the clock generator (G) is connected, that the output of the AND gate is conducted to a rectifier circuit (GR), that the AND gate, like the OR gate, is in each case provided with a capacitor (CT1, CT2) for maintaining a time-limited control potential, and that the clock generator (G) contains a KUJT flip flop circuit. If component faults occur, the programmed drop-out delay time of the circuit should only be shortened or disappear.