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Showing papers on "Gate driver published in 1982"


Proceedings ArticleDOI
M. Kamiya, Y. Kojima, Y. Kato, K. Tanaka, Y. Hayashi 
01 Jan 1982
TL;DR: In this paper, an n-channel EPROM with very high gate injection efficiency is described, which is called a perpendicularly accelerating channel injection MOS (PACMOS), which has a dual gate structure arranging a select-gate and a floating gate in series between the source and drain.
Abstract: An n-channel erasable and programmable read-only memory (EPROM) with very high gate injection efficiency is described, which we call a perpendicularly accelerating channel injection MOS (PACMOS). PACMOS has a dual gate structure arranging a select-gate and a floating gate in series between the source and drain. The select-gate and the floating gate are biased as to conduct the source and the drain potentials into two channels under the respective gate. The channel injection utilizes a channel potential gap built in at the boundary of these two channels. A fabricated PACMOS has shown that it can be programmed by voltage of 8V and current of 0.15µA, where a total injection efficiency (gate current /drain current) amounts to 10-3. It is considered that this very high gate injection efficiency is brought by the electron attractive field in the gate oxide under the floating gate.

68 citations


Patent
21 Jun 1982
TL;DR: In this article, a fast turn-off MOSFET circuit is provided by a JFET in the gate circuit of the MOSFCET which is connected to the same gate drive terminal as the MFSFCET.
Abstract: A fast turn-off MOSFET circuit is provided by a JFET in the gate circuit of the MOSFET which is connected to the same gate drive terminal as the MOSFET. The JFET becomes conductive upon turn-off of the MOSFET due to removal of gate drive. Conduction of the JFET provides faster discharge therethrough of residual stored charge on the MOSFET gate, whereby to facilitate faster MOSFET turn-off. A zener diode is connected in the gating circuitry and has a greater breakover voltage than the pinch-off voltage of the JFET, such that during turn-on, gate drive first pinches OFF the JFET and then charges up the MOSFET gate to drive the MOSFET into conduction.

44 citations


Journal ArticleDOI
TL;DR: In this article, a Josephson logic gate with a closed loop with four Josephson junctions (4JL gate) and its operating characteristics are described. But this is not the case for all 4JL gates with a minimum line width of 5 µm.
Abstract: A Josephson logic gate which consists of a closed loop with four Josephson junctions (4JL gate) and its operating characteristics are described. Devices have been fabricated using Pb-alloy technology with a minimum line-width of 5 µm. Gate operations with a current gain of 2 have been performed under complete input/output current isolation. A logic delay of 20 ps per gate has been measured in a chain of ten OR-gates for a fan-out of 1 with an average power dissipation of 3.7 µW.

30 citations


Patent
01 Apr 1982
TL;DR: In this article, a MOSFET-gated bipolar transistor and thyristor integrated devices combining, as the respective turn-on and turn-off control devices, an enhancement mode MOS-FET and a depletion mode MMSFET are connected to a single device gate terminal.
Abstract: MOSFET-gated bipolar transistor and thyristor integrated devices combining, as the respective turn-on and turn-off control devices, an enhancement mode MOSFET and a depletion mode MOSFET. The gates of the two MOSFETs are connected to a single device gate terminal. The conduction channel of the depletion mode MOSFET is preferably an implanted region. With gate voltage of appropriate polarity applied, the depletion mode MOSFET is non-conducting and the enhancement mode MOSFET is conducting, biasing the included bipolar transistor or thyristor into conduction. With zero gate voltage applied, the depletion mode MOSFET conducts and the enhancement mode MOSFET is non-conducting, turning off the included bipolar transistor or thyristor. Significantly, only a single polarity gate input signal is required.

25 citations


Patent
30 Sep 1982
TL;DR: An integrated circuit serving as an E/D type inverter circuit and provided with a gate-protection circuit is described in this article, where the gate of the D type MOSFET is protected by the gate protection circuit even if noise exists on the power supply line.
Abstract: An integrated circuit serving as an E/D type inverter circuit and provided with a gate-protection circuit The inverter circuit is constructed of an E type MOSFET having a gate coupled to an input signal and a D type MOSFET which operates as load, and the gate-protective circuit is constructed by a MOSFET which is connected between a power supply and the D type MOSFET and whose gate is connected to the power supply The gate of the D type MOSFET is protected by the gate-protection circuit even if noise exists on the power supply line

12 citations


Patent
15 Dec 1982
TL;DR: In this article, a stable NAND gate operation can be realized by introducing a NOR gate into all gate electrodes of the inputs of the NAND, except one gate electrode thereof of which source is grounded.
Abstract: In an integrated logic circuit employing normally-off type FET's, it is difficult, but desirable to realize a NAND gate due to unwanted flow of the forward current to the next stage. In accordance with the invention, a stable NAND gate operation can be realized by introducing a NOR gate into all gate electrodes of the inputs of the NAND gate, except one gate electrode thereof of which source is grounded.

11 citations


Patent
19 Nov 1982
TL;DR: In this paper, a feedback circuit is provided between the output and the input of a lower transistor amplifier of a push-pull amplifier driver output stage to inhibit power supply transients as the amplifier output stage transitions rapidly from a low to high output state.
Abstract: A feedback circuit is provided between the output and the input of a lower transistor amplifier of a push-pull amplifier driver output stage to inhibit power supply transients as the amplifier output stage transitions rapidly from a low to high output state. Additionally, if the push-pull output stage is incorporated within a three state gate or the like, which gate shares a common bus with other like three state gates, the feedback circuit inhibits loading of the bus whenever the three state gate is operated in a three state mode or is powered down as the other gates are active and are rapidly transitioned between low and high output states. The feedback circuit provides a low impedance path at the input of the lower transistor amplifier of the push-pull driver output stage to shunt transient currents harmlessly away from the base thereof to prevent the transient currents from turning on the lower transistor amplifier.

10 citations


Patent
15 Nov 1982
TL;DR: In this article, a high speed latch for integrated circuit applications employs a linear differential logic type gate and a cross coupled differential pair storage element which share common load terminals, and the linear differential pair is constrained to draw less current than the gate when there is contention between previously latched data and input data.
Abstract: A high speed latch for integrated circuit applications employs a linear differential logic type gate and a cross coupled differential pair storage element which share common load terminals. The cross coupled differential pair is transparent to the operation of the gate circuit in one condition and operative to store the current state of the gate circuit in another condition. The linear differential pair is constrained to draw less current than the gate when there is contention between previously latched data and input data. Thus, the linear differential pair does not inhibit operation of the gate when the gate is enabled. To provide the desired effect the gate uses a current source and the differential pair employs a resistor.

8 citations


Patent
Vincent G. Coppola1
14 May 1982
TL;DR: In this article, a bipolar driver is used to detect the presence of an illegal code combination which would otherwise function to simultaneously interconnect the load terminal with both positive and negative power supplies.
Abstract: A bipolar driver controls the operation of a reversible polarity load such as a motor. The driver links one terminal of the motor with either a positive or a negative potential power supply in response to processor command signals comprising a combination of logic levels appearing at a pair of driver input lines. The input lines are monitored to detect the presence of an illegal code combination which would otherwise function to simultaneously interconnect the load terminal with both positive and negative power supplies. The load terminal is linked to the power supplies by a separate power transistor for each power supply. Each power transistor is biased into conduction through a drive transistor. Upon detection of an illegal code, monitoring logic generates a signal which interrupts the emitter circuit of each of the drive transistors to inhibit both power transistors.

6 citations


Patent
23 Nov 1982
TL;DR: In this article, the authors propose to use a driver stage to split the digital input signal of a power stage to increase the source-gate voltage of one of the two field-effect transistors above its threshold voltage value.
Abstract: The control power input of a power stage designed in the form of a CMOS inverter can be considerably reduced according to the invention in that, with the aid of a driver stage splitting the digital input signal, each of the two gate electrodes of the two field-effect transistors of the power stage, are simultaneously but separately controlled by each time one driver signal of the same polarity, thus each time raising the source-gate voltage of one of the two field-effect transistors above its threshold voltage value.

4 citations


Patent
Erwin Jacobs1
09 Aug 1982
TL;DR: In this article, a double gate field effect transistor (DGFE transistor) is used as a selection element in a memory cell, where the first gate is a memory gate, whereas inversion layers are produced with the second gate electrode given supply of a gate voltage, extending the source and drain regions in the direction towards the memory gate.
Abstract: A memory cell comprises a double gate field effect transistor which exhibits source and drain regions located in a semiconductor body and two gate electrodes covering the semiconductor area between the source and drain regions, the gate electrodes being separated from the semiconductor body by a multilayer insulation. The first gate electrode is a memory gate, whereas inversion layers are produced with the second gate electrode given supply of a gate voltage, the inversion layers extending the source and drain regions in the direction towards the memory gate. The structure provides a surface-saving design of a selection element. The second gate electrode is employed for this purpose as the selection element and is connected to a selection line (word line). The invention finds application in very large scale integrated semiconductor memories.

Patent
25 Oct 1982
TL;DR: In this article, a dual bus driver including a voltage input, a current source, a single data input, and a first driver transistor for driving one bus, a second driver transistor for driving the other bus, and two differential transistors for turning on or disabling both driver transistors are presented.
Abstract: A dual bus driver including a voltage input, a current source, a single data input, a first driver transistor for driving one bus, a second driver transistor for driving the other bus, a first pair of differential transistors for turning on either the first driver transistor or the second driver transistor to couple an input signal at the data input to the one bus or the other bus, and a second pair of differential transistors for disabling both driver transistors. By providing a driver that drives both buses, reduced power consumption, fewer circuit components and less integrated circuit layout complexities are achieved.