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Showing papers on "Gate driver published in 1984"


Journal ArticleDOI
TL;DR: In this paper, a three-terminal power device, called the insulated gate transistor (IGT), with voltage-controlled output characteristics is described, where the best features of the existing families of bipolar devices and power MOSFET's are combined to achieve optimal device characteristics for low-frequency power-control applications.
Abstract: A new three-terminal power device, called the insulated gate transistor (IGT), with voltage-controlled output characteristics is described. In this device, the best features of the existing families of bipolar devices and power MOSFET's are combined to achieve optimal device characteristics for low-frequency power-control applications. Devices with 600-V blocking capability fabricated using a vertical DMOS process exhibit 20 times the conduction current density of an equivalent power MOSFET and five times that of an equivalent bipolar transistor operating at a current gain of 10. Typical gate turn-off times have been measured to range from 10 to 50 µs.

255 citations


Journal ArticleDOI
Renuka P. Jindal1
TL;DR: In this article, the effect of thermal voltage fluctuations in a resistive gate matrix perpendicular to the direction of channel current, in a MOSFET, is treated in detail, and a general formula is derived to arrive at channel current fluctuations for an arbitrary gate matrix layout.
Abstract: The effect of thermal voltage fluctuations in a resistive gate matrix perpendicular to the direction of channel current, in a MOSFET, are treated in detail. A general formula is derived to arrive at channel current fluctuations for an arbitrary gate matrix layout. This formulation is an extension of the analysis done by Thornber and is valid for frequencies at which the distributed RC time constants associated with the gate matrix are not important. The results of this analysis can be used to design low-noise resistive gate structures.

78 citations


Patent
27 Aug 1984
TL;DR: In this article, an isolating driver circuit between the PWM circuit and the control terminal of the power transistor comprises a low voltage power supply, a transformer having primary and secondary windings, an oscillator for outputting a high frequency signal, a MOSFET, means for rectifying the voltage in the secondary winding of the transformer and for applying the rectified voltage to the gate of the MOS FET, and switching means for rapidly discharging the gate when the high-frequency signal is no longer gated to the transformer.
Abstract: A switching amplifier comprises an input terminal connected to a d.c. power supply and an output terminal connected to a load. At least one power transistor is placed in series with the input and output terminals. A PWM circuit outputs a pulse width modulated signal. An isolating driver circuit between the PWM circuit and the control terminal of the power transistor comprises a low voltage power supply; a transformer having primary and secondary windings; an oscillator for outputting a high frequency signal; means for gating the high frequency signal from the oscillator to the primary winding of the transformer in response to the pulse width modulated signal from the PWM circuit; a MOSFET; means for rectifying the voltage in the secondary winding of the transformer and for applying the rectified voltage to the gate of the MOSFET; and switching means for rapidly discharging the gate of the MOSFET when the high frequency signal is no longer gated to the transformer.

49 citations


Patent
21 Feb 1984
TL;DR: In this paper, a power MOSFET is controlled by illuminating a single photovoltaic generator which produces an output current which charges the gate capacitanace of the power mOSFet to turn on the device.
Abstract: A power MOSFET is controlled by illuminating a single photovoltaic generator which produces an output current which charges the gate capacitanace of the power MOSFET to turn on the device. A sensing impedance which may be a diode, MOSFET or other component is connected between the photovoltaic generator and the gate of the power MOSFET. The sensing impedance in the disclosed embodiment is a diode. The sensing impedance forces the power MOSFET gate voltage instantaneously to follow the photovoltaic generator output voltage. The diode is connected in series with the charging circuit and a switching transistor is connected in parallel with the gate capacitance of the MOSFET. The switching transistior base is coupled to the output of the photovoltaic source so that, when the photovoltaic source turns off, and the voltage of the photovoltaic source decays below a predetermined value, the switching transistor turns on to short-circuit the MOSFET gate capacitance so that it can immediately discharge to provide fast turn-off of the power MOSFET. A dV/dt clamping circuit is provided to prevent false charging of the power MOSFET gate through its drain-to-gate capacitance.

38 citations


Journal ArticleDOI
TL;DR: In this paper, a novel circuit concept to reduce the gate loss using series capacitors on the gate feeding lines has been implemented for a distributed amplifier design, which significantly increased the gate width of the amplifier with a resultant increase of the broadband output power and efficiency.
Abstract: A novel circuit concept to reduce the gate loss using series capacitors on the gate feeding lines has been implemented for a distributed amplifier design. It has significantly increased the gate width of the amplifier with a resultant increase of the broadband output power and efficiency. A monolithic GaAs distributed amplifier using 6 x 300-micron FETs has achieved a record output power of 0.5 W over the 2 to 21 GHz frequency band with at least 4 dB gain. The power-added efficiency was 14 percent. The linear gain was 5 plus or minus 1 dB over the same frequency band.

25 citations


Patent
14 Dec 1984
TL;DR: In this paper, a semiconductor integrated circuit device in which the gate of a MOSFET of one circuit of the P channel MOS-FET is connected to the gate gate of the other circuit of N channel MCMOS-FCET is discussed.
Abstract: There is disclosed a semiconductor integrated circuit device in which the gate of a MOSFET of one circuit of the P channel MOSFET is connected to the gate of a MOSFET of the other circuit of the P channel MOSFET, and the gate of a MOSFET of one circuit of the N channel MOSFET is connected to the gate of a MOSFET of the other circuit of the N channel MOSFET.

11 citations


Patent
07 Mar 1984
TL;DR: In this article, a high power, high voltage linear field effect transistor amplifier apparatus utilizing an automatic gate biasing network to normalize the gate threshold voltages of a plurality of field effect transistors which are in either series or parallel is presented.
Abstract: A high power, high voltage linear field effect transistor amplifier apparatus utilizing an automatic gate biasing network to normalize the gate threshold voltages of a plurality of field effect transistors which are in either series or parallel Thus, these series or parallel combinations of field effect transistors may be operated as linear devices A high-voltage, high power, wide-band carrier controlled linear amplifier is provided by utilizing an oscillator as a driver

6 citations


Patent
11 May 1984
TL;DR: In this article, an input pulse with a high or low level is impressed to the input VIN3 and then the time when the TRs Q8 and Q9 turn on at the same time is shortened to reduce the through current of the output gate and also reduce the power consumption and power source noises.
Abstract: PURPOSE:To reduce the through current of an output gate and also reduce power consumption and power source noises without providing any extra gate in front of the output gate by applying an input pulse to gates of a PMOS and an NMOS transistors (TR) which constitute the output gate at the same time. CONSTITUTION:The gate VG8 of the P type MOSTRQ8 and the gate VG9 of the M type MOSTRQ9 of the complementary MOS logical gate are connected to an input VIN3 in common. Further, drains of the TRs Q8 and Q9 are connected to an output VOUT in common and the source of the TRQ9 is connected to a power source VSS. Further, the source of the TRQ8 is connected to the drain of an N type MOSTRQ7, whose source and gate are connected to a power source VDD in common. Then, the input pulse with a high or low level is impressed to the input VIN3 and then the time when the TRs Q8 and Q9 turn on at the same time is shortened to reduce the through current of the output gate and also reduce the power consumption and power source noises.

5 citations


Patent
Kazuo Suganuma1, Tsuneo Hamai1
24 Aug 1984
TL;DR: In this paper, a logic circuit consisting of a plurality of driver MOSFETs and one load MOSFLET produces an output signal responsive to input signals, which is a small area with low power consumption.
Abstract: A logic circuit, comprising a plurality of driver MOSFETs and one load MOSFET, produces an output signal responsive to input signals. The driver MOSFETs are each controlled by an input signal and the load MOSFET is controlled by one of input signals to conduct at opposite times to the driver MOSFET controlled by the same input signal. Therefore, a logic circuit with low power consumption and a small area is provided.

5 citations


Patent
31 Aug 1984
TL;DR: In this article, an injector constituted by an input diode connected to a column and a so-called control gate coupled to the column by a negativefeedback amplifier, characterised by the interposition between the said control gate and the input (G1) of the line memory, of at least one intermediate gate (Gp2) maintained at a fixed voltage.
Abstract: Line transfer light-sensitive device, of the kind comprising between each conductive column of a light-sensitive matrix and a corresponding input of a line memory, an injector constituted by an input diode connected to the column and a so-called control gate coupled to the column by a negative-feedback amplifier, characterised by the interposition between the said control gate (Gp1) and the input (G1) of the line memory, of at least one intermediate gate (Gp2) maintained at a fixed voltage. Such an intermediate gate allows regulation of the charge-flow regime whilst reducing the level of noise attributable to the action of the amplifier.

4 citations


Patent
30 Oct 1984
TL;DR: In this article, a kinescope driver stage in a television receiver includes an input pre-driver transistor and an output driver transistor arranged in a cascode amplifier configuration, and a capacitor is coupled from the signal input of the driver transistor to a point of reference potential.
Abstract: A kinescope driver stage in a television receiver includes an input pre-driver transistor and an output driver transistor arranged in a cascode amplifier configuration. To enhance the high frequency response of the driver stage, a capacitor is coupled from the signal input of the driver transistor to a point of reference potential.

Patent
17 Dec 1984
TL;DR: In this article, a semiconductor integrated circuit device in which the gate of a MOSFET of one circuit of the P channel MOS-FET is connected to the gate gate of the other circuit of N channel MCMOS-FCET is discussed.
Abstract: There is disclosed a semiconductor integrated circuit device in which the gate of a MOSFET of one circuit of the P channel MOSFET is connected to the gate of a MOSFET of the other circuit of the P channel MOSFET, and the gate of a MOSFET of one circuit of the N channel MOSFET is connected to the gate of a MOSFET of the other circuit of the N channel MOSFET.

Patent
16 Nov 1984
TL;DR: In this paper, the optimum control calculation of the entire water system including all dams and power generating stations of the water system in high speed altogether so as to attain the optimum controlling in following to the dynamic change in the water systems.
Abstract: PURPOSE:To simplify the control by the intervention of the operator by computing the optimum control calculation of the entire water system including all dams and power generating stations of the water system in high speed altogether so as to attain the optimum control in following to the dynamic change in the water system. CONSTITUTION:Plural power generating dams 1-3 are arranged in series from the upper stream to a river and reservoirs 4-6 are provided corresponding to the dams 1-3. Moreover, power generating stations 7-9 are installed to the dams 1-3 and power is generated by water stored in the reservoirs 4-6. Furthermore, water ways 13-15 are connected to the dams 1-3 so as to give ineffective effuluent to the reservoirs 4-6. Moreover, a power generating gate 16 and a direct effuluent gate 17 are provided to the dams 1-3 respectively and setting value controllers 18, 19 are installed to them. The controllers 18, 19 controls the gates 16, 17 so as to discharge set water flows W1, W2. The controllers 18, 19 are provided with a gate opening converter 24 converting the set water flow 20 into a gate opening 21 and a gate driver 25 outputting a motor drive signal 22 by using the opening 21 and gate opening information 23.

Patent
26 Sep 1984
TL;DR: In this article, the gate control triggering signal is inhibited in response to one of the detected unsafe conditions, and the gate driver inhibit is preferably sustained for a duration to allow normal turn-off of one thyristor before a second one.
Abstract: The control circuit includes a pair of switching circuits 14, 16 which measure the anode-cathode voltage and the current flowing through respective control thyristors 22, 24 of the inverter thereby to inhibit a gate control signal responsive to an on-off command signal when (i) the anode-cathode voltage falls below a predetermined value, (ii) the current flowing through the thyristor exceeds a predetermined unsafe level, or (iii) upon the occurrence of an inadequate power supply to the gate by circuits. The turn-off and turn-on delay periods of the thyristors may be complementary in duration thereby to assure complete turn-off of one thyristor before a second thyristor conducts in order to decrease the likelihood of short circuits across the poled thyristors. When the gate control triggering signal is inhibited in response to one of the detected unsafe conditions, the gate driver inhibit is preferably sustained for a duration to allow normal turn-off in response to the on-off command signal thereby to permit re- initialization of the power circuits of the gate driver. Also, sustaining of the inhibit condition permits sufficient time for a master control device to recognize the detection of the unsafe condition and to alter its state of operation accordingly.

Journal ArticleDOI
TL;DR: In this article, the authors proposed a new logic gate structure which consists of two semiconducting layers separated by an insulator, and the bottom conductive layer serves as a load.
Abstract: We propose a new logic gate structure which consists of two semiconducting layers separated by an insulator. The input electrode is a rectifying contact to the top conducting layer which acts as a channel of a switching field-effect transistor. The bottom conductive layer serves as a load. The conducting layers are connected and capacitively coupled. The top layer acts as a gate for the load element whereas the bottom layer acts as a second gate for the top conductive channel. This "folded" gate is a majority-carrier device which may be implemented using different technologies and materials. It allows a CMOS-like operation with a very low power consumption in the stable states, speed comparable or higher then the speed of conventional direct-coupled field-effect transistor logic (DCFL), and a larger voltage swing.