Showing papers on "Gate driver published in 1987"

Insulated gate bipolar transistor (IGBT) with a trench gate structure

Abstract: This paper describes an improved IGBT with a trench gate structure, which demonstrates a low forward voltage drop of 1.4 volts at a forward conduction current density of 200A/cm2. This device structure was fabricated using a self-aligned process that permits closely spaced vertical trench gates with a unit cell of 8 µm. This allows for a remarkable increase of channel density and elimination of the parasitic JFET effect thus reducing the forward voltage drop significantly. A static latching current density of 2700A/cm2has been achieved in the UMOS IGBT. Two-dimensional computer simulations of the UMOS IGBT has been performed to identify the optimal cell design. This optimal design is predicted to increase the SOA current density by a factor of 4.2 over the state-of-the-art DMOS IGBT at the same forward voltage drop.

Sense amplifier for a semiconductor memory device

Abstract: In a sense amplifier, the first input terminal of the differential amplifier (26) is connected to a first MOS transistor (23) operating as a transfer gate, a first floating gate transistor (22) operating as a memory cell, and a first load (24). The gates of the first MOS transistor (23) and the first floating gate transistor (22) are respectively connected to the column-­select line (BL) and the word line (WL). The second input terminal of the differential amplifier (26) is connected to a second load (28), a second MOS transistor (31) operating as a transfer gate, and a second floating gate transistor (32) operating as a dummy cell. The second load (28) has the same characteristics as the first load (24). The second load (28) is composed of first and second load elements (28A, 28B). The second floating gate transistor (32) is constantly supplied with power voltage. When a shift in the thre shold voltage of the first floating gate transistor (22) is monitored, the first load element (28A) of the second load (28) is disconnected from the input terminal of the differential amplifier (26), and only the second load element (28B) remains connected to the input ter­minal. The gate of the second MOS transistor (31) is supplied with the high potential. A gradually increas­ing potential is applied to the gates of the first MOS transistor (23) and the first floating gate transistor (22). The potential is detected when the data of the first floating gate transistor changes from "0" to "1".

A high-power high-gain VD-MOSFET operating at 900 MHz

Abstract: A new vertical double-diffused MOSFET (VD-MOSFET) capable of delivering output power of 100 W at 900 MHz has been developed. It offers the gain of 8 dB and the drain efficiency of 45 percent. The double diffusion self-aligned to the gate allows the devices to control the formation of the submicrometer channel essential for the high transconductance, hence the high gain, with minimum gate-to-source capacitance (C gs ). The device utilizes MoSi 2 for both gate electrodes and shield plates imbedded beneath the CVD oxide in the gate pad region. Low resistivity gate reduces the extra power dissipation to drive the gate, while the shield plate lowers the gate-to-drain capacitance (C gd ) to half. A maximum output power has been realized by the 12 blocks of VD-MOSFET's. They are mounted on the two BeO plates packaged with internal input matching circuits, and the power is measured in a push-pull amplifier.

Switch interface circuit for power mosfet gate drive control

Abstract: A switch interface circuit provides control voltages to the gate of a power MOSFET while protecting the power MOSFET from breakdown caused by transient signals and over-voltage. In one embodiment, a large JFET acts as gate-source shunt and a small JFET serves as a current source to turn the power MOSFET off when the turn-on current is removed. The JFET gate-drain and gate-source breakdown provides a voltage limitation to protect the MOSFET from gate overvoltage. Alternatively, Zener diodes and MOS transistors are used in lieu of the JFET for shorting the power MOSFET gate to source during turn-off and limiting its gate to source voltage during turn-on.

Column select circuit

Abstract: A column select circuit for a memory device is disclosed which, for unselected data lines, provides a high impedance output. Each data line, and a corresponding decoded address signal, is received by a gate which passes the logic state of the data line (inverted), if selected, to a driver. The decoded address signal is also communicated to the driver, for tri-stating the driver for unselected data lines. The driver consists of a p-channel pull-up and an n-channel pull-down, with an n-channel isolation transistor connected in series therebetween. The driver output is at the junction of the pull-up and isolation devices. The gates of the pull-up and pull-down transistors are connected to the output of the gate, with the gate providing a high logic level when not selected, turning off the pull-up device. The isolation transistor is also turned off when the data line is not selected, isolating the output from both the power supply node and ground, which allows the output to be pulled by photoconduction toward mid-rail in a transient radiation event. A plurality of gate/driver pairs are provided within a stage of the select circuit, each having their outputs connected together. The select circuit may be made up of a plurality of stages constructed as described above.

Hot standby amplifier apparatus

Abstract: The realization that field effect transistor current can be controlled by adjusting the gate voltage and thereby controlling the amplifier power consumption with only a slight degradation of RF gain and signal quality is utilized in a hot standby radio system configuration. The standby amplifier is left in an ON condition with the gate voltage adjusted to a low value until such time as the amplifier is needed for active service. At this time the gate voltage is adjusted to the optimal value and the amplifier is operated in a normal condition. The standby mode still allows tests to ascertain whether or not the amplifier is operational while conserving substantial amounts of power.

Linear power amplifying system

Abstract: A power MOSFET linear amplifier includes a plurality of paralleled MOSFETS having a gate-to-source resistor to ensure simultaneous turn-on and sharing of the load current. An arc lamp is connected in series with a 400 volt power supply and a variable ballast element in the form of the power MOSFET linear amplifier. The linear amplifier includes four similar modules. Each module is a hybrid circuit constructed with eight MOSFETs connected in parallel. Each MOSFET includes a similar gate-to-source resistor in addition to an appropriate gate resistor and source resistor. Under operating load current conditions, the gate-to-source resistors are laser trimmed to establish precise equalized current sharing in response to the specified operating input voltages. The module is set with the gate voltage slightly above the operating threshold voltage range of the MOSFET. The modules then operate with the essentially simultaneous turn-on of all MOSFETs and in a reliable balancing of current between the several MOSFET devices. The modules are fabricated with a common heat sink and an appropriate packaging for rapid dissipation of the heat, to thereby maintain the necessary low operating temperature which is essential to reliable operation of the MOSFET devices.

A low capacitance power MOSFET with an integral gate driver

Abstract: For efficient operation in the 10 MHz range, a resonant power converter needs a power MOSFET with very low capacitance for a given on-state resistance and an integral turn-off driver. The former allows the resonant frequency to be high and the gate drive losses low, while the latter avoids the parasitic inductance of bond wires used to connect the gate to an external driver. The reasons and methods for making such a MOSFET are presented in this paper.

Gate circuitry for hot box detectors

Abstract: A gating circuit and method for controlling the output of data from the scanner of a heat detector in response to a bi-polar signal indicating the presence of an object within the scanning window of the heat detector; stores the data output; senses the stored data with respect to a reference signal with a differential amplifier responsive to the data output; gates the data output to storage by a first gate interconnecting the data output with the differental amplifier; generates control signals for opening and closing the gate with different states of the bi-polar signal for controlling the gate such that the reference signal represents the last immediate data output; detects the difference between the stored peak value and the highest data value of the output data subsequent to turning off a first gate; and using a second gate interconnecting the output of the sensor with the detector and controlled by the control signals to be open with the first gate closed and closed with the first gate open

CMOS current sense amplifier

Abstract: A CMOS current sense amplifier is composed of an output inverter gate, a combined driver and biasing stage that biases the output inverter gate and drives its transistors, and an input stage that acts to reduce the input voltage swing. The circuit responds rapidly to input current changes and is therefore useful in sensing the currents in large memory arrays that have large shunt capacitance values.

Semiconductor differential amplifier

Abstract: A semiconductor differential amplifier includes first and second MOS transistors of a first conductivity type acting as driver transistors, and third through sixth MOS transistors of a second conductivity type acting as load transistors. First and second input terminals are respectively connected to gate terminals of the first and fifth, and second and sixth transistors. Therefore, since input signals are applied to transistors of both the load and driver sections of the amplifier, the amplifier exhibits a higher sensitivity for detecting relatively small differences between the voltage at the first input terminal and the voltage at the second input terminal.

Constant phase gain control circuit

Abstract: The disclosure relates to a dual gate FET 1 used in variable power amplifiers wherein a gain control circuit 7 is provided across the dual gate FET's electrodes G₁ and G₂ whereby the voltage on one of the gate electrodes is a function of the voltage on the other gate electrode.

Disconnectible semiconductor device, and its use

Abstract: In a semiconductor device which can be turned off by means of a first gate on the cathode side, a second gate structure comparable to the structure of the first gate is provided on the anode side. During turn-off, the charge carriers can be extracted more quickly from the base region of the device via the second, anode-side gate, thus improving the turn-off behaviour. At the same time, the novel device with double gate makes it possible to construct a double cascode circuit with two MOSFETs. … …

Device and method for testing controllable gate turn-off semiconductors for faults

Abstract: A fault in a gate turn-off thyristor (GTO) or a bipolar transistor is determined within the circuit, before an anode-cathode (collector-emitter) voltage is applied, by generating a gate pulse and monitoring the resultant gate (base) current. A fault in a gate turn-off thyristor almost always results in a short circuit between the gate-cathode terminals and between the anode-cathode terminals. The gate terminal can be interrupted in the case of other faults (idling state). The base-emitter path of a bipolar device can become faulty in a similar manner. Thus, the gate current which results from a gate pulse becomes abnormally large when the gate-cathode (base-emitter) terminals are short-circuited or the current is zero for an interrupted circuit or for a gate driver fault.

A high-voltage integrated circuit for power supply applications

Abstract: A new high-voltage integrated circuit (HVIC) is described which controls either PWM or Resonant half-bridge circuit topologies for power supply applications at frequencies up to 1 MHz. The HVIC technology allows the two power FETs in half-bridge circuit arrangements to be driven from a single silicon chip thus eliminating external, isolated gate drivers. Isolation for the "upper" FET gate driver is achieved on-chip using the HVIC technology. Communication with the "upper" gate drive is also achieved with an on-chip high voltage transistor operated as a current source. The chip has the usual power supply control functions (including current-mode control) as well as a voltage-controlled oscillator (VCO) for resonant converter control. In addition, a novel pulse detector circuit is included to allow the chip to receive isolated pulses from a secondary side control, thus achieving simple digital isolation between primary and secondary.

Driving method for protecting MOS power transistors on inductive loads

Abstract: With the aim of reducing the expenditure for protecting the MOS power transistors by the protection being taken over by the drive for the gate signal, this driving method, in which the current flows inversely from source to drain at least at times, is characterised by the fact that the gate is turned off in such a manner that, in a first process, the gate is discharged via an electronic switch, this switch is then opened again and when the drain voltage rises, the gate of the transistor is charged up via a capacitor voltage divider in order to put the transistor partly into a conducting state, and then the gate is discharged in a short time after a drain voltage of 1-50 % of the turn-off voltage has been reached.

Switch array device

Abstract: PURPOSE:To prevent the S/N of a read signal from being deteriorated due to the variation of the conductance of a switch means by providing a reset bias means resetting a level of each parallel input signal and a level of a common signal line and a common line to a bias potential by which the input/output characteristic of the 1st and 2nd read means has a linearity before the input signal is transmitted. CONSTITUTION:Each capacitor of a capacitor section 7 is connected respectively to transmission switch elements 6 connected in common at each block to store the electric charge transferred through the switch elements 6. Further, the titled device is provided with a power supply 8 applying a drive voltage to the photoelectric conversion element, a gate driver 9 to activate the switch elements 5, 6, a reset bias 10 fed to the reset switch element 6 to reset the charge storage capacitor, a switch array 11 to output serially the electric charge transmitted to the capacitor section 7, and a differential amplifier 112 connected to two output terminals of the switch array 11.

Multi-value memory

Abstract: PURPOSE:To suppress noise generated by the change of a data line voltage and to write with high accuracy by making different the driving waveform of the data line at the time of writing, between data line pairs. CONSTITUTION:By an address signal a0, a signal phiX is changed over 41 and sent to a common line 48 and connected to a word line 7 to add the reading writing voltage to a memory cell column 1 by the output of a decoder 35. Reading 33 or writing 32 is executed through a data line 20. The signal charge is supplied from a mechanism 37 and the suitable resetting gate is operated. By a writing gate driver 47 and a temporary memory circuit 34, the writing timing signal is generated, a writing gate 120 is selected and the voltage before writing is set 110. Synchronizing to one of voltages generated by a means 39, on the data line, a voltage VD different before and after the timing is added and the prescribed relation with other data line is kept. By such a constitution, the noise of the capacity coupling characteristic occurring at the time of writing is significantly reduced and the memory device of the super high integration can be obtained.

Turn-off control circuit for a gate turn-off thyristor

Abstract: A turn-off control circuit for a gate turn-off thyristor is used in a state where one end of an inductive load is connected therewith on the cathode side. The turn-off control circuit includes a first turning-off transistor, which takes-out electric current through the gate at the first stage of the turn-off operation of the gate turn-off thyristor, and a second turning-off transistor, which takes-out electric current through the gate at the second stage of the turn-off operation of the gate turn-off thyristor so as to surely effect the turn-off operation.

Device physics and modeling of integrated power devices

Abstract: In a field where the last new device, the Gate Turn-off Thyristor was invented over 25 years ago, the invention of no fewer than four new MOS controlled devices in under 10 years represents a dramatic change and rebirth. In this paper four MOS gated power switching devices are reviewed; the Insulated Gate Transistor (IGT), the Lateral IGT (LIGT), the MOS Controlled Thyristor (MCT), and the trench gate power MOSFET. These devices come singularily closer to ideal switches than any of their predecessors because of their combination of low conduction losses and ease of gating through their MOS gates. Much of the progress on these new devices has been greatly aided by the use of numerical device simulations, particularly since the physics of the devices are quite complex. The paper will serve to acquaint the reader with the properties of these devices as well as with the results of the device simulations and their role in the device development.