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Showing papers on "Gate driver published in 1988"


Journal ArticleDOI
01 Apr 1988
TL;DR: A review of the evolution of a power transistor technology based on MOS gate control is provided in this article, which offers the advantage of very high input impedance, which allows the control of the devices using low-cost integrated circuits.
Abstract: A review of the innovations that have led to the evolution of a power transistor technology based on MOS gate control is provided. This technology offers the advantage of very high input impedance, which allows the control of the devices using low-cost integrated circuits. The physics of operation of the two types of devices in this category, power MOSFETs and power MOS-bipolar devices, are described. Trends in process technology and device ratings are analyzed. Based on the superior performance of these devices, it is projected that they will completely displace the power bipolar transistor in the future. >

75 citations


Patent
23 May 1988
TL;DR: In this article, a gate driver circuit is provided for push-pull power transistors and a voltage clamping circuit is used to prevent the negative transition from exceeding a predetermined limit.
Abstract: A gate driver circuit is provided for push-pull power transistors. Inverse square wave signals are provided to each of the driver circuits for activating the power transistors. The combination of an inductor and diodes provides a delay for activating the corresponding power transistor at a positive transition of the control signal, but do not have a significant delay at the negative transition. This provides protection to prevent the power transistors from being activated concurrently while having lower power loss at high drive frequencies. The control terminal for each power transistor is connected to a voltage clamping circuit to prevent the negative transition from exceeding a predetermined limit.

46 citations


Patent
07 Mar 1988
TL;DR: In this paper, a control circuit for a full bridge switching converter including power FET switching devices is presented, including a gate driver with a voltage sensor circuit, which senses the precise instant to gate the power switch on in order to achieve substantially lossless switching by the converter.
Abstract: A control circuit for a full bridge switching converter including power FET switching devices. The control circuit including a gate driver with a voltage sensor circuit which senses the precise instant to gate the power FET on in order to achieve substantially lossless switching by the converter.

41 citations


Patent
10 Mar 1988
TL;DR: In this article, a circuit is proposed to reduce the amplitude of ringing on a bus, due to rapid discharging of current from the bus, in order to prevent unintentional triggering of devices connected to the bus.
Abstract: A circuit is provided which modifies a digital drive signal to produce a time variant drive signal for application to a gate of a bus driver transistor. The circuit's purpose is to reduce the amplitude of ringing on a bus, due to rapid discharging of current from the bus, in order to prevent unintentional triggering of devices connected to the bus. A P-channel MOS transistor and N-channel MOS transistor are connected so that the digital drive signal is simultaneously applied to the source of the P-channel MOS transistor and to the drain of the N-channel MOS transistor. The gate of the driver transistor is connected to the drain of the P-channel MOS transistor and the source of the N-channel transistor. The width-to-length ratio of the channels of the P-channel and N-channel MOS transistors, and the gate voltages, are chosen so that application of a drive signal to the circuit causes the N-channel MOS transistor to rapidly apply a limited drive signal to the gate of the driver transistor and causes the P-channel MOS transistor to apply a gradually increasing drive signal voltage to the gate of the driver transistor. By choosing the proper width-to-length ratios and gate voltages, the time variant drive signal applied to the gate of the driver transistor will not produce objectionable ringing on the bus when the bus is intended to be at a low level.

34 citations


Patent
James J. Komiak1
01 Dec 1988
TL;DR: In this paper, a digitally controlled variable power amplifier for radio frequency signals is proposed, which is used to drive the individual elements of a phased array radar system in which accurate tapering of the power supplied to individual antenna elements is desired for sidelobe control in the face of jamming and other circumstances.
Abstract: The invention relates to a digitally controlled variable power amplifier for radio frequency signals. The power amplifier has application to power amplifiers for driving the individual elements of a phased array radar system in which accurate tapering of the power supplied to individual antenna elements is desired for sidelobe control in the face of jamming and other circumstances. In this application, each power amplifier must maintain a stable phase transfer response and should remain at a high power transfer efficiency at each reduced power setting. This performance is achieved by the use of a power transistor of a segmented dual gate design. The segments of the second gate electrode are of digitally scaled widths and are individually energized to activate digitally scaled regions of the transistor. These regions are operated in a saturated class "A" mode in all power settings to achieve the desired stable phase transfer response and high power added efficiency.

34 citations


Patent
08 Apr 1988
TL;DR: In this paper, a MOSFET bus driver transistor (11) has a gate to drain capacitance (C GD ), which substantially dominates other capacitances at the gate terminal.
Abstract: A transmitter circuit (10) for transmitting a digital data signal over a bus line (14) in a digital data processing system includes a MOSFET bus driver transistor (11) having a gate to drain capacitance (C GD ) which substantially dominates other capacitances at the gate terminal. The bus driver transistor (11) is driven by a buffer circuit (12) having pull-up and pull-down transistors (16, 17), the current through which is controlled by current sources (20, 21). The gate terminal of the driver transistor (11) is connected to, and controlled by, the node (22) between the pull-up and pull-down transistors (16, 17). The drain terminal of the driver transistor (11) is connected to, and controls, a bus line (14). To assert a signal on the bus line (14), the pull-up transistor is turned on to drive current into the node (22) at a rate governed by the current source (20), which increases the voltage level of the node (22). When the voltage level of the node (22) reaches the driver transistor's threshold level, the driver transistor (11) begins to turn on, allowing the voltage level of the bus line (14) to drop. Contemporaneously, current flows into the node (22) from the bus line (14) through the driver transistor's high gate to drain capacitance (C GD ), thereby limiting the voltage level of the node (22), and thus the current flow through the driver transistor (11). Thus, current flows through the driver transistor (11) from the bus line (14) in a manner controlled, in part, by the voltage level on the bus line (14). In negating a signal on the bus line (14), the operations are similar, with current flowing out of the node (22) through the pull-down transistor (17) and the driver transistor's gate to drain capacitance (C GD ).

27 citations


Patent
George J. Korsh1, Edward S. Hui1
09 Sep 1988
TL;DR: In this article, a transistor construction with a gate electrode meandering in a serpentine manner between interlacked comb-like drain and sources electrodes is described. The construction is equivalent to parallel transistors with series-connected gates, and the resistivity of the gate electrode forms a RC delay line in which transistors furthest from the gate drivers lag behind those which are closest.
Abstract: A transistor construction having a gate electrode meandering in a serpentine manner between interlacked comb-like drain and sources electrodes. The construction is equivalent to parallel transistors with series-connected gates, and the resistivity of the gate electrode forms a RC delay line in which transistors furthest from the gate drivers lag behind those which are closest. Accordingly, the transistor construction turns on or off gradually. The construction is useful as part of a CMOS output driver to memory chips and the like where the inductance of bondwires and the package leads normally cause noise spikes. The transistor construction reduces the current slew rate during switching so that less noise occurs on the chip supply lines. Another embodiment is made up of up to four parallel connected blocks of series-connected-gates. Multiple gate turn-off drivers are provided in a modified output driver, connected in parallel to each series-connected gate block, to insure that the transistor block turns off more rapidly than it turns on.

25 citations


Patent
30 Aug 1988
TL;DR: In this paper, an output driver circuit is described which can be programmed by the user into tri-state or open-collector configurations, depending on the needs of the user.
Abstract: An output driver circuit is described which can be programmed by the user into tri-state or open-collector configurations, depending on the needs of the user The driver circuit comprises a pair of a first pull-up and a pull-down FET transistor The source of the pull-up transistor and drain of the pull-down transistor are both connected to the output of the driver The gates of the pair of transistors are controlled by an input signal and its complement The driver further includes a second pull-up FET whose source is connected to the output of the driver The channel width to channel length ratio of the second pull-up transistor is at least about an order of magnitude greater than that of the first pull-up transistor The driver further includes a control means responsive to the input signal for applying a second signal to the gate of the second pull-up transistor for programming the driver into tri-state or open-collector modes The driver circuit may be controlled by the output of an OR gate in an AND-OR array in a FPLA or PAL device The driver is programmable by programming the AND gate or OR gate array and applying selected input signals to the AND gate array; the driver can also be programmed permanently into the tri-state or open-collector mode

24 citations


Patent
19 Sep 1988
TL;DR: In this article, a power MOS transistor includes a polycrystalline silicon layer which provides connection to act as a resistor between a first portion of gate metallization disposed above the gate of the device, and a second part of gate metalization adjacent to the active source/gate region.
Abstract: A power MOS transistor includes a polycrystalline silicon layer which provides connection to act as a resistor between a first portion of gate metallization disposed above the gate of the device, and a second portion of gate metalization adjacent to the active source/gate region of the device.

21 citations


Patent
16 Nov 1988
TL;DR: In this article, an insulated gate semiconductor switch, such as a MOSFET, produces a notch in the gate voltage for an interval B following an interval A after initial application of a gate control voltage pulse for turning the switch on, and a notch for interval C following termination of the gate controller voltage pulse followed by interval D during which the switch is turned on again.
Abstract: Energy is recovered from an insulated gate semiconductor switch, such as a MOSFET, that is otherwise lost in the gate capacitance by producing a notch in the gate control voltage for an interval B following an interval A after initial application of a gate control voltage pulse for turning the switch on, and a notch for an interval C following termination of the gate control voltage pulse followed by interval D during which the switch is turned on again, where each interval is a period ΔT given by ##EQU1## L s is the inductance (discrete and/or parasitic) in series with the gate electrode of the insulated gate semiconductor switch, and C in is the capacitance of that switch between its gate and source electrodes. The interval ΔT may be provided directly by timing in a pulse forming circuit for the gate control voltage applied, or adaptively by sensing the gate voltage v g and comparing it with fixed progressively higher voltages v 1 , v 2 and v 3 , where v 2 is intermediate v 1 and v 3 which correspond to the lower and upper levels of v g as the switch is turned off and on.

20 citations


Proceedings ArticleDOI
P. Saunier1, H.Q. Tserng1, N. Camilleri1, K. Bradshaw1, H. D. Shih1 
06 Nov 1988
TL;DR: In this article, a three-stage Ka-band GaAs FET power amplifier was designed and fabricated on MBE (molecular-beam epitaxy)-grown material with a highly doped (8*10/sup 17/ cm/sup -3/) channel.
Abstract: A monolithic three-stage Ka-band GaAs FET power amplifier has been designed and fabricated on MBE (molecular-beam epitaxy)-grown material with a highly doped (8*10/sup 17/ cm/sup -3/) channel. Devices with gate length of 0.25 mu m and gate width of 50 mu m, 100 mu m, and 250 mu m were cascaded. The gate and drain bias networks were also integrated. A maximum small-signal gain of 26 dB was obtained with 4 V on the drain and 0 V on the gate. When biased for large-signal operation, the amplifier was capable of generating 112 mW output power with 16-dB gain and 21.6% power-added efficiency at 34 GHz. It is believed that this is a record efficiency for a GaAs MMIC (microwave monolithic integrated circuit) amplifier at this frequency. >

Patent
Kouichi Kaneko1
05 Feb 1988
TL;DR: In this article, a failure detecting gate circuit for bus signal lines is presented, which is a multiplexer which outputs one of two signals indicating either a failure condition or a normal signal provided by the microcontroller.
Abstract: A failure detecting gate circuit for bus signal lines. The gate circuit include gate elements connected to each bus line and controlled by control signal, and a processing unit which controls any one of the gate elements. The processing unit operates to switch the gate elements to an "ON" state when the control signals are supplied to the gate elements of each gate. The failure detecting circuit outputs an indication signal of a failure condition in the processing unit. This occurs when control signals are supplied, such that at least two gate elements are to be switched to the "ON" state simultaneously. The improvement of the present invention over previous devices is a multiplexer which outputs one of two signals indicating either a failure condition or a normal signal provided by the microcontroller.

Patent
Chung Hyung-Sob1
16 Sep 1988
TL;DR: In this article, a dual-slope waveform generation circuit without a DC path and with decreased layout area including a pull-up and pull-down resistor, a transmission gate and an inverter.
Abstract: A dual-slope waveform generation circuit without a DC path and with decreased layout area including a pull-up and pull-down resistor, a transmission gate and an inverter. An input signal IN is applied to the pull-up transistor, to each gates of MOS transistors M 1 , M 2 composing of the inverter A, and to drains of MOS transistors M 3 , M 4 composing of the transmission gate B. A common node in the inverter is connected to the gate of the N type MOS transistor in the transmission gate. The sources of the transistors M 3 , M 4 are connected to the gate of the pull-down transistor. An output signal OUT is applied to the gate of the transistor M 4 and the signal is fed back.

Patent
07 Oct 1988
TL;DR: In this article, a gate control circuit is proposed to provide gate bias for both power MOSFETs from a single gate bias provided between first and second nodes for serial connection to a supply-and-load circuit.
Abstract: A bidirectional MOSFET switching circuit employs a pair of common-drain-connected power MOSFETs whose sources are connected to respective nodes for serial connection to a supply-and-load circuit. A gate control circuit provides gate bias for both power MOSFETs from a single gate bias provided between first and second nodes. The gate control circuit includes a pair of common-source-connected control MOSFETs with their sources connected to the first node; with their drains respectively connected to the respective gates of the power MOSFETs; and with their gates connected in common to the second node and to the common-connected drains of the power MOSFETs. The gate bias is preferably provided by a photovoltaic initiator circuit which can be integrated into a monolithic IC along with the power MOSFETs and control circuit.

Proceedings ArticleDOI
02 Oct 1988
TL;DR: In this article, the authors study the short-circuit capability of IGBTs and show that the high current level or active region of the IGBT is different for different manufacturers.
Abstract: The IGBT (insulated-gate bipolar transistor) or COMFET (conductivity-modulated field-effect transistor) has the same low drive requirements as for MOSFETs and the same carrier injection as a bipolar transistor, giving a low voltage drop even at high breakdown voltage ratings. The authors study the short-circuit capability. The high-current level or active region is found for different IGBTs. The short-circuit endurance time is investigated. The measurements show clear differences between the IGBTs from different manufacturers. The gate voltage is shown to be an important parameter. >

Patent
02 Dec 1988
TL;DR: The antibounce circuit as mentioned in this paper consists of a first flip-flop constituted by a first and a second NAND gate (10, 12) having their respective outputs connected to one of the inputs of the other gate, the free input of the first gate being the input for said digital signal.
Abstract: The antibounce circuit comprises: (a) a first flip-flop constituted by a first and a second NAND gate (10, 12) having their respective outputs connected to one of the inputs of the other gate, the free input of the first gate being the input for said digital signal; (b) a second flip-flop constituted by a third and fourth NAND gate (14, 16) having their respective outputs connected to one of the inputs of the other gate, the free input of the third gate being connected to the output of the first gate; (c) a non-inverting delay circuit (20, 22, 24) connecting the output of the third gate to the free input of the second gate; (d) a first inverter connecting the output of the delay circuit to the free input of the fourth gate.

Patent
29 Aug 1988
TL;DR: In this article, a power switch MOSFET (insulated gate field effect transistor) is switched from an OFF state to an ON state, a switching element SW is temporarily turned to the ON state and the drain of the Q1 is connected with the gate.
Abstract: PURPOSE: To accelerate switching speed while simplifying a power switch circuit by providing a switch means, etc., to transmit the drain voltage of a power switch MOSFET temporarily to a gate corresponding to the signal change of an input signal. CONSTITUTION: When a power switch MOSFET (insulated gate field effect transistor) Q1 is switched from an OFF state to an ON state, a switching element SW is temporarily turned to the ON state and the drain of the Q1 is connected with the gate. Namely, the gate capacity of a comparatively large capacity value provided in the Q1 is rapidly executed by a power supply voltage VDD of the Q1 itself through a load and the Q1 is switched from the OFF state to the ON state at high speed. At such a time, an input current to be supplied to an input terminal G can be made small corresponding to the input currents of an amplifier circuit AMP and a pulse generating circuit PG. Accordingly, the circuit AMP forms only a gate voltage required for practically maintaining the Q1 in the ON state and the circuit can be simplified by using a logic IC, etc. Then, high-speed switch control can be executed. COPYRIGHT: (C)1991,JPO&Japio

Journal ArticleDOI
01 Oct 1988
TL;DR: In this article, the authors show that self-heating of continuously operated transistors increases the output slope conductance in practical applications, and this is quantitatively to be in agreement with temperature-dependent theory.
Abstract: Improved (constant current) output characteristics of the insulated gate bipolar transistor are theoretically attainable by reducing the minority carrier diffusion length, but the improvements are only observable in practice with low duty cycle or cold (isothermal) curve tracer characteristics. The self-heating of continuously operated transistors increases the output slope conductance in practical applications, and this is shown quantitatively to be in agreement with temperature-dependent theory. The desirable feature of a high output slope resistance of such a MOS-bipolar power device can be adjusted in a controllable manner by application of substrate (body) feedback to a MOSFET driver. This method, which avoids interference with the input impedance of the control gate, has been tested using discrete components in order to demonstrate the feasibility for an integrated power module.

Patent
18 Oct 1988
TL;DR: In this paper, a fault-resistant, solid-state line driver with a pair of P-type transistors in series between a bus output and a voltage source, and a pair N-types transistors connecting the bus output to the connection to ground is presented.
Abstract: A fault-resistant, solid-state line driver having a pair of P-type transistors in series between a bus output and a voltage source, a pair of N-type transistors in series between the bus output and a connection to ground, and a pair of input lines, one of the input lines being connected to both the gate of the P-type transistor closest to the voltage source and the gate of the N-type transistor closest to the bus output, the other input line being connected to both the gate of the P-type transistor closest to the bus output and the gate of the N-type transistor closest to the connection to ground. Such a line driver is particularly useful in devices utilizing wafer-scale levels of integration, as the failure of any one of the driver's transistors will not result in a shorting of the bus output to either ground or the voltage source.

Patent
16 Jan 1988
TL;DR: In this paper, the collector terminals of first and second transistors (off gate elements) Tr1 and Tr2 are connected with the gate terminals of a power switching element SIT through resistances R1 and R2, and the resistance R1 is set to a value sufficiently smaller than the resistance R2.
Abstract: PURPOSE: To shorten a storage time without reducing a fall time and to make a switching action into high speed and high frequency by providing first and second off gate elements. CONSTITUTION: The collector terminals of first and second transistors (off gate elements) Tr1 and Tr2 are connected with the gate terminals of a power switching element SIT through resistances R1 and R2, and the resistance R1 is set to a value sufficiently smaller than the resistance R2. When an off signal is outputted to an input terminal t2, the transistors Tr1 and Tr2 are simultaneously turned on. While the transistor Tr1 is turned on based on the time constant of a capacitor C and a resistance R3, a gate current Ig1 flows much in a reverse direction, and little gate current Ig1 flows in the same direction by the collector current of the transistor Tr2 after the transistor Tr1 is turned off. Thus, the storage time can be shortened while the prescribed fall time is secured. COPYRIGHT: (C)1989,JPO&Japio

Patent
12 Feb 1988
TL;DR: A power MOS transistor includes a polycrystalline silicon layer (18) which provides connection to act as a resistor between the first portion (26) of gate metallization disposed above the gate of the device, and the second portion (28) adjacent to the active source/gate region as mentioned in this paper.
Abstract: A power MOS transistor includes a polycrystalline silicon layer (18) which provides connection to act as a resistor between the first portion (26) of gate metallization disposed above the gate of the device, and a second portion (28) of gate metallization adjacent to the active source/gate region of the device.

Patent
15 Mar 1988
TL;DR: In this paper, a common collector-amplifier level shifter circuitry was proposed, which imposes no current load on the preceding amplifier stage associated with its level shifters, and can be incorporated in apparatus for supplying constant current loading to the preceding stage, having a source of constant current connected to its input connection.
Abstract: Level shifter circuitry, as for an operational amplifier, imposes no current load on the preceding amplifier stage associated with its level shifter function. A common-collector-amplifier first transistor has base and emitter connections to the input and output terminals of the level shifter. A second transistor of similar conductivity type and common-collector forward current gain has its base electrode connected through a first current mirror amplifier to the input terminal of the level shifter and has its emitter electrode connected through a second current mirror amplifier to the output terminal of the level shifter. The first and second current mirror amplifiers have similar current gains. The first current mirror amplifier may also be incorporated in apparatus for supplying constant current loading to the preceding amplifier stage, to this end having a source of constant current connected to its input connection.

Patent
10 Feb 1988
TL;DR: An insulated gate bipolar transistor (IGBT) as discussed by the authors incorporates a base contact (40a,40b) usable with an external circuit for depleting charge from the base (18) when stopping bipolar conduction.
Abstract: An insulated gate bipolar transistor (IGBT) device incorporates a base contact (40a,40b) usable with an external circuit for depleting charge from the base (18) when stopping bipolar conduction, thereby increasing turn-off speed. Fabrication of the IGBT is described.

Patent
03 Jun 1988
TL;DR: In this paper, a gate series resistor made of a specific material between a gate drawing electrode and a gate bonding pad was proposed to reduce the number of circuit parts, increase the packaging density, and facilitate the design of a circuit.
Abstract: PURPOSE: To achieve high-density circuit packaging and simplify circuit design, by interposing a gate series resistor made of a specific material between a gate drawing electrode and a gate bonding pad CONSTITUTION: A gate electrode formed in an interlayer insulating films of an MIS type field effect transistor chip 1 is drawn outside by a gate lead elec trode 6 A gate bonding pad 7 to connect the electrode 6 to the outside is formed in a part of the electrode 6 A gate series resistor 8, made of the same material as that of the gate electrode and having a resistivity different from the gate electrode, is formed between the electrodes 6 and 7 The resistor 8 placed on the chip 1 enables directly connecting a driving IC with an MIS to protect the driving IC and prevent spike voltage from being produced Compounding the resistor 8 from the same material as the gate electrode and building the resistor 8 in the MISFET 1 decreases the number of circuit parts, increase the packaging density, and facilitates the design of a circuit COPYRIGHT: (C)1989,JPO&Japio

Proceedings ArticleDOI
J. Thoma1, F. Pavuza
09 May 1988
TL;DR: In this paper, the switching performance of power MOSFETs as a function of the input characteristics is described, and the model introduced describes the effects of the propagation delay of the gate signal.
Abstract: The switching performance of power MOSFETs as a function of the input characteristics is described. The use of highly doped silicon gate material together with a voltage-dependent shunt input capacitance results in a single cell resembling a transmission line element. Thus the MOSFET chip can be described as a two-dimensional line. Since the switching performance is a function of the input voltage, the form of the transmitted gate-trigger pulse mirrors the switching performance of the structure. The model introduced describes the effects of the propagation delay of the gate signal. It can be used to show the effects of the on-chip delay of the applied gate voltage on the surface of a single MOSFET as well as on discrete paralleled cells comprising the vertical power MOSFET. >