Showing papers on "Gate driver published in 1990"

Self-adjusting impedance matching driver

Abstract: A self-adjusting impedance matching driver for a digital circuit. The driver has both a pull-up gate to VDD and a pull-down gate to ground. An array of gates is provided in parallel with each of the pull-up gate and the pull-down gate, with any one or more of such gates being selectively enabled in response to circuit means that monitors the impedance match between the output of the driver and the network it drives. By enabling selectively such gates, any impedance mismatch can be minimized. The selective enablement may be done only at power up, and thereafter only if the driven network is changed substantially.

An investigation of the drive circuit requirements for the power insulated gate bipolar transistor (IGBT)

Abstract: The drive circuit requirements of the OGBT are explained with the aid of an analytical model. This model can be used to describe the turn-on and turn-off, gate and anode, current and voltage waveforms for general external drive, load, and feedback circuits. It is shown that nonquasi-static effects limit the influence of the drive circuit on the time rate-of-change of the anode voltage. Model results are compared with measured turn-on and turn-off waveforms for different drive, load, and feedback circuits and for different IGBT base lifetimes. The effective output capacitance of the IGBT at turn-off is several orders of magnitude larger than that of the structurally equivalent power MOSFET and depends upon the device base lifetime because the base charge at turn-off depends upon the device base lifetime. However, the gate drain feedback capacitance is unchanged from the value for the structurally equivalent power MOSFET. Thus, the minimum gate resistance that influences the anode voltage rate-of-rise at turn-off is several orders of magnitude larger than that for the power MOSFET and varies with device base lifetime. >

Sample-and-hold switch with low on resistance and reduced charge injection

Abstract: An improved sample-and-hold circuit includes a first MOSFET transmission gate connected between an analog input voltage and a storage capacitor. The first transmission gate is constructed to have low on resistance and operates for a predetermined period of time to rapidly charge the capacitor to input voltage. A second, smaller MOSFET transmission gate having reduced charge injection characteristics is connected in parallel with the first gate. The second gate is turned on coincidentally with the first gate but remains on for a short period of time after the first gate has been switched off.

Semiconductor memory device having flip-flop circuits

Abstract: A semiconductor static random access memory having a high α-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.

Compensation of the gate loading loss for travelling wave power amplifiers

Abstract: The disclosure relates to a circuit to reduce the gate loss in a semiconductor travelling wave power amplifier using series capacitors on the gate feeding lines for a distributed amplifier design. The circuit arrangement significantly increases the gate width of the amplifier with a resultant increases of the broadband output power and efficiency.

Transformer coupled gate drive circuit for power MOSFETS

Abstract: A driving circuit, for switching devices such as power MOSFETs, Insulated Gate Bipolar Transistors and the like, includes a transformer with a primary winding which receives input control signals having positive and negative portions. The driving circuit responds to the control pulses from the secondary winding of the transformer to charge a storage capacitor during the positive portions of the control signals. A pair of low power switching devices, i.e., MOSFETS, are turned on mutually exclusively by the control signals. A first one of the low power MOSFETs is turned on during the positive portion of the control signals to clamp the gate voltage of and keep the power MOSFET turned off and at the same time to enable electrical charge to flow from the control pulse to the storage capacitor. During the subsequent negative portion, the first transistor is turned off and the second transistor is turned on to allow electrical charge to flow from the storage capacitor to the gate of the power MOSFET.

Ground bounce limiting driver using non-linear capacitor

Abstract: A ground-bounce limiting circuit comprised of a non-linear Miller capacitance between the drain and the gate of an output driver. Ground-bound is limited by controlling the time-ramping of the output current by continuously diverting the charge at critical times and thresholds on the gate of the output driver which are being delivered by a predriver.

A 2000 V-non-punch-through-IGBT with dynamical properties like a 1000 V-IGBT

Abstract: A 2000-V IGBT (insulated-gate bipolar transistor) based on the simple concept of the non-punch-through IGBT is presented The devices were processed on bulk silicon material without any lifetime-killing steps On-state voltage and turn-off losses are nearly the same as for 1000-V IGBTs The forward-bias safe-operating area of the devices is a rectangle up to 1800 V; no latchup occurs up to the short-circuit saturation current >

Nand cell type programmable read-only memory with common control gate driver circuit

Abstract: A NAND cell type EEPROM has a substrate, parallel bit lines formed above the substrate, and a memory cell section including an array of NAND type cell units associated with the same corresponding bit line. Each of the NAND type cell units has a series-circuit of eight data storage transistors and at least one selection transistor. Each data storage transistor has a floating gate for storing carriers injected thereinto by tunneling and a control gate respectively connected to word lines. A control gate driver circuit is provided in common for all the NAND type cell units that are assisted with the same bit line. Transfer gates are connected between the common driver circuit and the NAND cell units.

Bicmos logic circuit for basic applications

Abstract: In one embodiment of the invention, an inverter inverts an input signal and provides this inverted input signal into the base of an NPN bipolar transistor, acting as a pull-up device, whose collector is coupled to a positive power supply voltage. The input signal coupled to the input of the inverter is also coupled to the gate of a large N-channel MOSFET, acting as a pull-down device, having its drain coupled to the emitter of the bipolar transistor and its source coupled to ground. The common node of the bipolar transistor and the N-channel MOSFET provides the output signal of the driver. This driver uses much less area than a standard two-bipolar transistor BiCMOS driver with substantially equal performance. A small P-channel MOSFET having its gate connected to the input signal may be connected across the base and emitter of the bipolar transistor to provide a full output voltage at the output of the driver.

Gate-resistance-limited switching frequencies of power MOSFETs

Abstract: High-frequency switching limitation of a power MOSFET resulting from large gate resistance is studied. It is shown that a maximum gate switching frequency can be identified to minimize resistive power dissipation in the gate. Power MOSFETs with refractory silicide gates are shown to result in more than a fivefold improvement in this frequency compared to conventional heavily POCl/sub 3/-doped polysilicon-gated MOSFETs with metal gate runners. >

Comparative analysis of power bipolar devices

Abstract: A comparison between bipolar Darlington, insulated gate bipolar transistor (IGBT), bipolar mode field effect transistor (BMFET), and power MOS devices is presented based on an experimental investigation performed on devices with similar geometrical characteristics and blocking voltage capabilities. The main device characteristics (conduction characteristics, switching performances, power dissipation, power ratings, etc.) are presented and compared in order to obtain comprehensive guidelines for finding their fields of application. It is shown that, for higher frequency switching application, MOS devices are the most suitable, but they are very expensive in terms of silicon area used. For frequencies less than 20 kHZ, BMFETs have better performance than IGBTs in terms of power losses. On the other hand, the IGBT is a voltage-controlled device and thus has fewer problems with its driving circuit. >

Accurate characterization of gate resistance and high-frequency switching efficiency of a power MOSFET

Abstract: Accurate gate resistance measurement of advanced high-density power MOSFET technology is reported. Calorimetric gate power loss measurement using sinusoidal input signals shows that more than a fivefold reduction in gate resistance can be achieved by employing refractory metal/silicide gate and contact technologies. A further reduction in gate resistance was measured for power MOSFETs with integral Schottky diodes. A simple analysis is presented to relate power loss components to power FET die size and switching frequency. Using this formulation, a study of the output current-handling capability of a power device is made, and it is correlated with power conversion frequency. The results of this analysis, when applied to silicided power MOSFETs, suggest that gate silicidation can improve power-handling capability of a conventional power MOSFET by a factor of two. A reduction in gate resistance is shown to improve the maximum switching frequency. Silicidation of gate polysilicon is shown to improve the frequency bandwidth of a power MOSFET by more than a factor of five. >

Mos-type integrated circuit

Abstract: In a MOS-type integrated circuit, a source and a gate of a double diffusion MOSFET of an n-channel type and a drain and a gate of a double diffusion MOSFET of a p-channel type are in an island region surrounded by an n-type annular contact region having high impurity concentration. An n epitaxial layer, in each island region, is used for the sources and drains of both MOSFETs. The drain electrode of the p-channel MOSFET is connected to the gate electrode of the n-channel MOSFET. With this structure, the power consumption of the circuit is decreased, and the operating speed thereof is increased.

Liquid crystal display device and video signal recording and reproducing device

Abstract: PURPOSE: To reproduce a still picture at low cost with simple constitution by providing an active matrix LCD, a driver which turns on and off switching elements, and a control circuit, and supplying no scanning pulse to the switching elements at least a period wherein a still picture can be recognized. CONSTITUTION: The active matrix LCD 15 which has display elements and switching elements at respective display positions is driven by a gate driver 11 and a source driver 13. The active matrix LCD 15 is supplied with a video signal through the switching elements, and the switching elements of the respective picture elements are driven by drivers such as a gate driver. When the still picture reproduced, a control circuit 20 controls, for example, a 2nd driver to stop generating scanning pulses for several seconds. Consequently, the active matrix LCD holds the signals of the respective picture elements as they are and can reproduce the still picture without using any frame memory. COPYRIGHT: (C)1991,JPO&Japio

Timed current boost for dmost driver with rapid turn-on and low quiescent current

Abstract: A power DMOST driver employs a diff-amp gate driver (14) that operates at a relatively low quiescent current when the DMOST (13) is on Means are included for switching the DMOST (13) off and on in response to a control signal When the DMOST (13) is to be switched from off to on the diff-amp tail current (I₁) is briefly raised to a substantially higher value so that the DMOST parasitic gate capacitance (21,22) can quickly be driven to the on level The tail current differential is large and determined by geometrically controlled IC quantities

HIGH FREQUENCY 6000 V DOUBLE GATE GTOs WITH BURIED GATE STRUCTURE

Abstract: A new double gate GTO with buried gate structure for a second gate has been proposed to realize high turn-off gain simultaneously with low turn-off switching loss. The double gate GTO has been combined with an n-buffer structure to realize 6000 V forward blocking voltage with a narrow n-base width, such as 550 p. The high turn-off gain, such as 6, was obtained when the anode current was 500 A. It was found that the double gate GTOs with buried gate realize a very short tail time and a small tail current. The newly developed double gate GTOs decrease the turn-off loss to less than 1/10 of that for the conventional single gate GTOs.

Self-powered scr gate drive circuit with optical isolation

Abstract: The improved gate drive circuit provides a continuous gate current whenever there is sufficient anode-to-cathode voltage difference across the SCR. This approach described herein eliminates the need to monitor and reapply SCR gate current after each commutation due to load current distortions. Previous SCR gate driver designs used a pulse train of gate currents to provide a means of keeping the SCRs turned on. The pulsed gate control approach has gaps in the SCR's operation and requires significant circuitry that dissipates much more drive energy. Energy for this improved driver circuit is derived from the SCR anode-to-cathode voltage differential. This eliminates the need for individual power supplies to provide isolated gate signals for each SCR. This self-powering feature reduces the intricacy of controlling multiple SCRs in multi-phase or unreferenced power systems. Flexibility provided by this method allows high power SCRs to be directly interfaced to a digital processor-type controller.

Electric apparatus for vehicle having induction device of stater/generator

Abstract: PURPOSE: To raise an efficiency of an electric apparatus for a vehicle, by using an asynchronous induction unit having both starter and generator functions. CONSTITUTION: A PWM generator 36 executes a sine function search, and gives six PWM drive signals of low level (5 volts) to a gate driver 38 in channels 56 to 66 according to energizing amplitude and power frequency control signals A, POWERF given by a system control unit 34. The driver 38 drives a switching unit of a bidirectional bridge circuit 26. The circuit 26 is constituted to control 3-phase full-wave currents of an induction unit 18. In crank start mode, the circuit 26 energizes 3-phase windings of the unit 18 by a sine wave current having predetermined amplitude and frequency from a battery 12. In a generating mode, the circuit 26 leads a sine waveform load current having predetermined amplitude and frequency from the unit 18.

A low energy drive for high power 300 A-1000 V IGBT

Abstract: A new concept for the IGBT (insulated gate bipolar transistor) drive circuit is described. This driver requires few components and draws little power. It is totally insulated, making it very interesting for building inverter legs. The driver performs well over the 50 Hz to 500 kHz range (more than is needed for IGBT-based power converters). Bistable operation allows for a very small pulse transformer even in the bottom end frequencies. The driving energy is transferred to the IGBT input capacity in a resonant mode. A prototype was built, and circuit operation is shown on oscilloscope plots. >

Turn-off circuit for gate turn off SCR

Abstract: Turn-off of a GTO-SCR with substantially reduced tail current is achieved by means of a controlled switching circuit coupled to the both the anode gate and the cathode gate of the thyristor. When operated, the switching circuit simultaneously removes current from the cathode gate and injects current into the anode gate, thereby completely removing stored charge. The controlled switching circuit preferably comprises a transistor the collector-emitter path of which bridges the anode and the anode gate of the GTO SCR, and injects anode gate current at the same time that current is being removed from the cathode gate. Control of the base drive to the bridging transistor may be effected by a current mirror drive circuit referenced to the cathode gate of a turn-off control thyristor.

Gate-driver circuit

Abstract: PURPOSE:To compact the title circuit, and to improve profitability by installing two pairs of signal processing circuits composed of an oscillator, an AND circuit, a FET and a small-sized high-frequency transformer and the like. CONSTITUTION:A gate-driver circuit for driving an inverter at high speed consists of a processing circuit 1 for two pairs of driving signals, the transmission circuit 2 of the driving signals and the transmission circuit 3 of a set signal and an output circuit 4 to the gate terminal of a FET 22 as a semiconductor switching element. Outputs from AND circuits 7-8 from the driving signal 5 and oscillator 6 of the processing circuit 1 are input to the gate terminals of the FETs 9-10 of the transmission circuit 2, and output to the output circuit 4 from the secondary sides of high-frequency transformers 12-13. Accordingly, a switching rate is increased, thus acquiring high gains.

Comparison of MOS devices for high frequency inverters

Abstract: The switching performances of power MOSFETs, insulated gate bipolar transistors (IGBTs), and two types of MOS-controlled thyristors (MCT) are evaluated and compared The devices all have a similar forward blocking voltage rating of near 1 kV and current ratings that were matched as closely as possible All the devices were operated up to their maximum possible frequency It is shown that, below several hundred kilohertz switching frequency, a power MOSFET is undesirable because of the extremely large forward voltage drop and the need for parallel operation during high current switching applications and that, above 500 kHz, the MOSFETs are the only devices that can operate effectively Also, it is shown that the IGBTs operate effectively up to about 200 or 300 kHz, the fairly long turn-off limits their ability to function at higher frequencies, and the MCTs are limited to switching below about 50 to 100 kHz >

A low energy drive for high power 300 A-1000 V IGBT

Abstract: An insulated-gate bipolar transistor gate driver circuit that requires few components, is easy to implement, is totally insulated and performs well over the range of 10 Hz to 600 kHz is described. It is shown that the reduction of driver power consumption results in a reduction of the power supplies and that the low component number and the reduced transformer provide a very compact circuit, making integration possible. The circuit performance and operation are discussed. >

A 500-MHz monolithic CRT video driver using a linear array

Abstract: A 500-MHz bandwidth, high-precision monolithic video driver IC for the next-generation leading CRT display with 4 Mpixels or more is described. Based on a novel circuitry design, the driver IC was fabricated by a 2.5- mu m complementary-bipolar-transistor array. It has a multi-output current amplifier, a gain controller, a video multiplexer, and a sample-and-hold bias circuit. The IC realizes a new wide-bandwidth (250-300 MHz) CRT video amplifier scheme; a current-mirror-driven cascade amplifier with a low-voltage feedback is used for DC restore. >

Study of negative bias on the IGBT's gate

Abstract: A negative gate bias during the IGBT's (insulated gate bipolar transistor's) turn off modifies the switching parameters. This effect is highlighted and analyzed. Unlike the MOS transistor, the IGBT's turn-off behavior at high frequency with negative gate bias shows a strong inversion layer at the oxide-n-semiconductor interface. A simplified model is used to show the improvements in delay time and current and voltage switching speeds brought about by the negative gate bias. The negative bias can reduce the turn-off losses by 25%. >

The cmos column decorder involving static moving

Abstract: The decoder for making output of I/O gate zero without the help of auxiliary clock signals when I/O gate is not selected includes a main decoder (302) for inputting decoding clock signals (0AI,0AJ,0AK) to PMOS transistors (201,202,203) and NMOS transistors (109,110,111) and for driving I/O gates (300,300',300", 300"',303,303',303",303"') according to the decoding clock signals, and an I/O gate driver (301) for driving I/O gates (300,303) when signals of I/O gate drivers is not selected utilizing the output signals of main decoder and decoding clock signals.

A fully-protected bipolar MOSFET controller

Abstract: A description is given of a fully protected bipolar MOSFET controller which is designed to drive and protect current-sensing or standard DMOS (double-diffused metal-oxide-semiconductor) field-effect transistors in either high-side or low-side configurations. The IC is designed for use in automotive environments, and therefore protects both the discrete MOSFET and the driver IC from overvoltage, overtemperature, and short-circuit conditions. The circuit operates from 4.5 to 28 V, draws 20- mu A off-state current, and gives diagnostic feedback via an error pin. >

BICMOS driving stage for a class AB output gate in integrated circuits

Abstract: The present invention relates to a BICMOS driving stage for a class AB output gate in integrated circuits which comprises an operational amplifier and an output gate. The operational amplifier is connected to the output gate by means of at least one N-channel transistor (24) the drain terminal whereof is connected to the gate terminal. The drain and gate terminals define an electric node to which the gate terminal of an N-channel transistor (27) is connected. The drain terminal of the N-channel transistor is connected to a node which is defined by the collector and base terminals of an NPN transistor (28) of the output gate.