Showing papers on "Gate driver published in 1996"

A capacitive threshold-logic gate

Abstract: A dense and fast threshold-logic gate with a very high fan-in capacity is described. The gate performs sum-of-product and thresholding operations in an architecture comprising a poly-to-poly capacitor array and an inverter chain. The Boolean function performed by the gate is soft programmable. This is accomplished by adjusting the threshold with a dc voltage. Essentially, the operation is dynamic and thus, requires periodic reset. However, the gate can evaluate multiple input vectors in between two successive reset phases because evaluation is nondestructive. Asynchronous operation is, therefore, possible. The paper presents an electrical analysis of the gate, identifies its limitations, and describes a test chip containing four different gates of fan-in 30, 62, 127, and 255. Experimental results confirming proper functionality in all these gates are given, and applications in arithmetic and logic function blocks are described.

Transformer isolated driver for power transistor using frequency switching as the control signal

Abstract: A driver for a power transistor (a MOSFET or IGBT) uses a transformer to isolate the power supply from the control signal, but uses very low power components on the isolated side to allow use of a physically small transformer. The control signal is one of two frequencies, and the isolated side of the driver includes a circuit for detecting which of the two frequencies is present. One frequency is preferably twice as much as the other. The output of the frequency detection circuit switches between low and high states depending on the frequency present, and the output of this circuit is connected to the input of a transistor driver circuit which charges the gate of the power transistor.

MOS gate driver circuit with analog input and variable dead time band

Abstract: A MOS gate drive (MGD) integrated circuit drives a pair of MOS gated power semiconductor devices such as are used in a half bridge circuit to drive a load in a resonant power supply circuit or to drive a gas discharge lamp in a ballast circuit. The gate drive circuit includes dead time circuitry which prevents simultaneous conduction in both MOS gated devices. The duration of the dead time is controlled in response to a feedback signal that is sensed from the output supplied to the load or the lamp. A dimming function is attained by controlling the voltage of the feedback signal.

Display and method of and drive circuit for driving the display

Abstract: A display has a display panel of a first aspect ratio and is able to display on the display panel an image of a second aspect ratio whose width element is larger than that of the first aspect ratio. The display has a gate driver, a data driver, and a timing controller. The gate driver sequentially selects gate lines of the display panel. The data driver stores data for one gate line and supplies the data to one of the gate lines selected by the gate driver. The timing controller supplies control signals to the gate and data drivers so that predetermined data is displayed in top and bottom non-image areas of the display panel during a vertical blanking period. The display is capable of displaying images of different sizes.

Bidirectional blocking accumulation-mode trench power MOSFET

Abstract: One or more diodes are (J1, J2, J3) integrated with a trenched gate accumulation-mode MOSFET to provide protection for the gate oxide layer. In a preferred embodiment, a first pair of diodes (J2, J3) are formed in a series connection between the source(s) and the gate (61) of the MOSFET. A third diode (J1) may be added to provide a series diode pair (J1, J3) between the drain (64) and the gate (61) of the MOSFET. A pair of accumulation-mode MOSFETs may be formed in a single chip to provide a push-pull halfbridge circuit, and a multiple-phase motor driver may be fabricated in two chips, with the high side MOSFETs being formed in one chip and the low side MOSFETs being formed in the other chip. The accumulation-mode MOSFET may be used as an AC switch by connecting its gate to a gate bias circuit which finds the lower of the source and drain voltages of the accumulation-mode MOSFET.

Power application circuits utilizing bidirectional insulated gate bipolar transistor

Abstract: A matrix converter utilizes a bidirectional lateral insulated gate bipolar transistor (IGBT) including two gate electrodes. The IGBT can conduct in two directions. The matrix converter preferably is a three phase matrix converter including nine bidirectional IGBT switches. The IGBT switches are controlled by a control circuit which includes eighteen control lines, two for each IGBT. Additionally, the bidirectional IGBT can be used in a precharge circuit of a power inverter or in a dynamic brake associated with a motor controller.

Method of making an ultra high density NAND gate using a stacked transistor arrangement

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of a lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor. In addition to the inverted, shared gate conductor, the multi-level transistor fabrication process incorporates formation of openings and filling of those openings to produce interconnect to junctions of the upper/lower transistors. Interconnecting the gate conductors of a pair of stacked transistors and connecting specific junctions of those transistors allows development of a high density NAND gate. The NAND gate includes two pairs of stacked transistors, wherein one transistor of a pair can be connected to the other transistor of that pair or connected to one or both transistors of the other pair.

Surge and overcurrent limiting circuit for power converters

Abstract: Current flow between the boost inductor and the output bulk capacitor in a boost converter type power factor correction circuit for an AC-to-DC power converter is controlled by a single power MOSFET which is operated by a gate driver in a low-level constant current surge limiting mode during initial charging of the bulk capacitor, and in a high-level current-limiting mode once the bulk capacitor is sufficiently charged for normal operation. The power MOSFET gate driver is in turn controlled by a control logic which is connected to the input and output voltages of the boost converter, and which allows the circuit to cope with short circuits and input power interruptions and glitches.

Bidirectional lateral insulated gate bipolar transistor

Abstract: A bidirectional lateral insulated gate bipolar transistor (IGBT) includes two gate electrodes. The IGBT can conduct current in two directions. The IGBT relies on a RESURF operation to provide high voltage blocking in both directions. The IGBT is symmetrical, having N-type drift region in contact with an oxide layer. A P-type region is provided above the N-type-drift region, having a portion more heavily doped with P-type dopants. The RESURF operation can be provided by a buried oxide layer or by a P substrate or by a horizontal PN junction. The IGBT can be utilized in various power operations, including a matrix switch or a voltage source converter.

Ultra high density NOR gate using a stacked transistor arrangement

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of a lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor. In addition to the inverted, shared gate conductor, the multi-level transistor fabrication process incorporates formation of openings and filling of those openings to produce interconnect to junctions of the upper/lower transistors. Interconnecting the gate conductors of a pair of stacked transistors and connecting specific junctions of those transistors allow development of a high density NOR gate. The NOR gate includes two pairs of stacked transistors, wherein one transistor of a pair can be connected to the other transistor of that pair or connected to one or both transistors of the other pair.

Driver circuit including preslewing circuit for improved slew rate control

Abstract: A preslewing circuit to rapidly drop a voltage on the gate of a power device in a power stage has a combination of a bipolar transistor and CMOS transistors. The gate voltage is brought down by the preslewing circuit to a level at which an output voltage can begin to change. The combination has high conduction and can be integrated readily, with good internal isolation, in a small chip area, thus having qualities desirable for high performance, integrated, driver circuits.

Intrinsic element sensing integrated SOA protection for power MOSFET switches

Abstract: A protective circuit for a power field effect transistor, e.g., a power MOSFET, employs a diode-switched pickup circuit, a threshold detector, and a timer. The pickup circuit includes a resistor and diode in series, with the diode connected with the MOSFET drain electrode and the resistor connected with the gate driver for the MOSFET gate electrode. A pickup voltage V 1 appears at the junction of the diode and resistor. When the MOSFET is conducting the pickup voltage is the sum of the channel voltage V ds-on and the diode forward voltage V f . When the MOSFET is biased OFF, the pickup voltage is zero. The threshold detector compares the pickup voltage with a reference voltage that is offset some predetermined amount from the source electrode voltage. When threshold circuit goes high, the timer circuit provides a time-out or inhibit signal to an inhibit input of the gate driver circuit. Under high load current or high temperature conditions, the drain-source voltage V ds-on rises, and if the threshold is exceeded, the gate signal is cut off. This holds the transistor OFF for the timer period. This arrangement uses the MOSFET channel resistance R ds as the current sense resistor. The protective circuit can be integrated, and can be combined with the MOSFET in a single package.

High performance gate drives for utilizing the IGBT in the active region

Abstract: The advantages of operating the IGBT in its active region for active snubbing and series operation have been established in the literature. In this paper we describe the implementation and performance of several gate drive circuits suitable for use in closed loop control of the IGBT voltage. The application of the gate drives to active control of a wide range of IGBT devices is demonstrated and discussed.

An isolated MOSFET gate driver

Abstract: Traditional methods of isolated MOSFET/IGBT gate drive are presented, and their pros and cons assessed. The best options are chosen to meet our objective— a small, high speed, low cost, low power isolated gate drive module. Two small ferrite bead transformers are used for isolation, one transmits power at 2.5MHz, the other sends narrow set reset pulses. On the secondary these pulses drive a transistor totem pole to ensure high current drive, and the value is held by CMOS buffers with positive feedback. An alternative design for driving logic level devices uses only an HC buffer on the secondary. Double sided SMDconstruction (primary one side, secondary on the other) yields an upright module 40x18x5mm. Propagation delaywas 20ns, and rise/fall time 15ns with a 1nF load. The design places no limits on frequency of operation or duty cycle. Power supply requirementswere 5V@20mA for operation below 100kHz, dominated by magnetising current.

The series connection of IGBTs investigated by experiments and simulation

Abstract: Both, experimental and simulation techniques are used to investigate the series connection of IGBTs. An experimental setup with a power rating of 4.8 kV and 600 A is established. Circuit simulations are performed using physics-based models for the IGBT and the freewheeling diode. Experimental and calculated characteristics agree very well.

Using floating gate devices as select gate devices for NAND flash memory and its bias scheme

Abstract: The present invention facilitates programming of selected floating gate devices while successfully inhibiting the programming of unselected devices, without the need for growing multiple thicknesses of oxides. The preferred embodiment of the present invention utilizes a multiple select gate device. In particular, the select gate device is preferably a dual floating gate device rather than the conventional transistor (or device functioning as a conventional transistor) used in the current Flash memory systems as a select gate device.

Measurement of a cross-section for single-event gate rupture in power MOSFETs

Abstract: The heavy-ion fluence required to induce Single-Event Gate Rupture (SEGR) in power MOSFETs is measured as a function of the drain bias, V/sub DS/, and as a function of the gate bias, V/sub GS/. These experiments reveal the abrupt nature of the SEGR-voltage threshold. In addition, the concepts of cross-section, threshold, and saturation in the SEGR phenomenon are introduced. This experimental technique provides a convenient method to quantify heavy-ion effects in power MOSFETs.

Assessment of off-state negative gate voltage requirements for IGBTs

Abstract: This paper addresses the need for off-state negative gate bias with insulated gate bipolar transistor (IGBT) devices that experience a dv/dt when in the off state. Factors considered include off-state gate bias voltage, gate impedance, reapplied dv/dt, and temperature. Theoretical calculation and experimental results for a high-voltage high-current IGBT supports the assessment of these factors.

Switch driver circuit

Abstract: A driver circuit for a semiconductor power switch. The driver circuit supplies a high voltage pulse to the gate of an IGBT. The driver circuit also monitors the voltage on the collector of the IGBT with respect to the emitter. If the voltage at the collector of the IGBT does not drop when the IGBT is turned on, the IGBT driver circuit detects a short circuit and triggers a linear integrator within the driver circuit. The linear integrator gently ramps down the voltage on the gate of the IGBT.

Dielectrically isolated power IC

Abstract: A power IC having at least a level shifter for changing the level of an input signal, a high-side driver circuit for driving a predetermined load in accordance with a level changed by the level shifter, the high-side driver circuit being in a floating state, and a reverse current preventing diode for disconnecting a current path from the ground of the level shifter to the reference potential of the high-side driver circuit. The high-side driver circuit and reverse current preventing diode are respectively dielectrically isolated by a dielectric member to prevent insufficient element isolation to be caused by bias conditions. The predetermined reference potential to be connected to an inductive load or the like in the high-side driver circuit can be set to a negative potential. The electrical energy stored in the inductive load or the like can be extracted out and attenuated at high speed via the reference potential set to the negative potential to thereby realize a high speed operation.

Drive circuit of self-quenching-type semiconductor device

Abstract: PROBLEM TO BE SOLVED: To suppress di/dt and dV/di while preventing the increase in time delay of the switching in a voltage-controlled-type self-quenching-type semiconductor device such as an IGBT(Insulation Gate Bipolar Transistor). SOLUTION: A switching circuit 6 tums on a transistor 8 (10) based on the ON (OFF) signal of an ON/OFF signal 101 and applies a power supply 15 (16) to the gate of an IGBT 25 via a low-value gate resistor 12 (14). Then, the gate capacity of the IGBT is rapidly charged (discharged) and at the same time VGB increases (decreases), and current Ic begins to increase (decrease) with a small delay time. At this point, a voltage 106 is generated at an inductance 36 being connected between an auxiliary emitter terminal Es and a main emitter terminal Em of the IGBT 25, thus activating a one-short circuit 32 (33). A switching circuit 6 turns off the transistors 8 (10) and 7 (9) due to the one-shot output 102 (103) at this point, switches a gate resistance to 11 (13) with a larger value and relaxes the rising (trailing) speed of Ic.

High-speed main amplifier with reduced access and output disable time periods

Abstract: An output buffer is provided to output data read out from a memory array. The output buffer is composed of a main amplifier and an output driver. An input latch stage of the main amplifier is connected to an output of a preamplifier that reads out data from the memory array. A level shifter is coupled to the input latch stage to drive one of transistors in a transistor pair of the output driver. A driver stage is coupled to the input latch stage to drive another transistor in the output driver transistor pair. An output enable signal is supplied to the level shifter and to the driver stage to control the output driver. When the output enable signal is set to a first logic level, the output driver supplies valid data to an external device. When the output enable signal is at a second logic level, the output of the output driver is brought to a floating high-impedance state to disable data output.

Driving device and driving method for a thin film transistor liquid crystal display

Abstract: A driving device and a method of driving a TFT-LCD uses a two-pulse electrode voltage to thereby double the duration of the driving impulse. The driving device includes a liquid crystal interface IC which outputs a two-pulse start signal and a clock signal. A gate bus driver IC outputs a two-pulse gate electrode voltage to each gate line according to the start signal inputted from the liquid crystal interface IC and a liquid crystal pixel is driven by the difference in potential between a grey voltage and a common electrode voltage after the TFT in each gate line is driven by the two-pulse gate electrode voltage input from the gate bus driver IC.

Liquid crystal display devices having redundant gate line driver circuits therein which can be selectively disabled

Abstract: A liquid crystal display including a driving circuit is provided. The LCD in which one gate line is driven by both left and right gate drivers includes a couple of switching means which are placed between the gate driver and gate line, the couple of switching means being activated and deactivated by switching control signals to switch the output of the gate driver. When one of the gate drivers does not operate, the output of the gate driver having the operational problem is prevented from being applied to the gate lines, by a switching operation. Therefore, even when only one of gate drivers operates, the display panel can function properly, thereby preventing the lowering of picture quality and improving product yield.

Control gate driver circuit for a non-volatile memory and memory using same

Abstract: A control gate driver circuit (900) provides a variety of voltages to a control gate (21) of a floating gate nonvolatile memory cell (10) using a single circuit. During a read mode, a bias circuit (920) and a reference transistor (925) bias a pass transistor (936) connected to the output of a level shifter (910) to be slightly conductive and thus biases control gates without the need for a charge pump. During programming, a pulse circuit (940) gradually builds the program voltage provided to cells along a selected row, allowing the use of smaller pass transistors (932, 934) and smaller capacitors in the charge pump of the supply (930). Cells in an unselected row are driven to a different voltage, decreasing junction leakage and maintaining high disturb voltage in cells in the unselected row. The control gate driver circuit (900) is implemented using only P-channel pass transistors, eliminating the need for a costly triple-well process.

Microwave amplifier circuit

Abstract: A microwave amplifier circuit includes an amplifier having a gate to which a microwave signal is input and an output terminal from which an amplified signal is output, and a gate bias resistor having a variable resistance connected between the gate of the amplifier and a gate bias terminal for controlling a voltage applied to the gate while maintaining a constant bias voltage at the gate. Even when variations occur in the threshold voltage of the amplifier because of process variations, the gain of the circuit can be held constant, without the bias voltage being adjusted, so that yield is improved.

Implementation of high peak-current IGBT gate drive circuits in VLSI compatible BiCMOS technology

Abstract: A BiCMOS integrated gate-drive (IGD) application specific integrated circuit (ASIC) has been implemented in a 18 V, 3 /spl mu/m BiCMOS technology for insulated gate bipolar transistor- (IGBT-) based intelligent power modules (IPM). It features various monitoring and control functions such as linear dV/dt feedback and master-slave control of IGBT's, and is capable of delivering 16-18 A peak current to high capacitive loads. Classic formulas on the current capability of bipolar junction transistors (BJT's), MOSFET's, and metal conductors are briefly reviewed and additional experiments are presented in the context of our application.

Linearization of voltage-controlled amplifier using MOSFET gain control circuit

Abstract: A linearized voltage controlled amplifier (VCA) circuit uses the resistance of a gain control MOSFET to control amplifier gain in accordance with a DC gain control voltage. A gain control voltage is applied to the gain control MOSFET's gate through a gate input resistor that forms a voltage divider with a feedback resistor from the output of the amplifier. Since the VCA's output terminal is a low impedance node, the voltage divider network applies most of the gain control voltage to the gate of the gain control MOSFET. Conversely, a small fraction of the amplifier output signal is coupled to the gain control MOSFET's gate, to reduce distortion. The linearized VCA circuit is augmented by a gate drive correction circuit, through which the gain control voltage is coupled to the VCA's gain control MOSFET. The gate drive correction circuit is comprised of a difference amplifier and a compensating MOSFET that is matched with the gain control MOSFET of the VCA circuit for controlling its gate drive voltage.

Open drain output driver having digital slew rate control

Abstract: An open drain driver circuit includes first and second NMOS driver transistors, a delay circuit, an OR gate and an AND gate. Each NMOS driver transistor has a drain coupled to an output terminal, a source coupled to a supply terminal, and a gate. The delay circuit has an input coupled to the input terminal and has an output. The OR gate has a first input coupled to the input terminal, a second input coupled to the output of the delay circuit and an output coupled to the gate of the first NMOS transistor. The AND gate has a first input coupled to the input terminal, a second input coupled to the output of the delay circuit and an output coupled to the gate of the second NMOS transistor.

Master-slave bistable latch with clock input control

Abstract: It is an object to obtain a semiconductor integrated circuit with reduced power consumption without reducing operation speed. In clock input control means (27), an exclusive OR gate (26a) receives comparison data (S1 and S2) and an NAND gate (27a) receives output of the exclusive OR gate (26a) and a reference clock (T) and outputs its output, a control signal (SC1) to an AND gate (G1) and an AND gate (G2) in a data holding portion (31a). An exclusive OR gate (26b) receives comparison data (S3 and S4) and an NAND gate (27b) receives the output of the exclusive OR gate (26b) and the reference clock (T), and outputs its output, a control signal (SC2) to an OR gate (G5) and an OR gate (G6) in a data holding portion (31b). Appropriately selecting the comparison data (S1-S4) allows data transfer at high speed of input data (D), output data (Q), inverted output data (QC), and so forth.