Showing papers on "Gate driver published in 2009"

15.2: Development of Driver‐Integrated Panel Using Amorphous In‐Ga‐Zn‐Oxide TFT

Abstract: We designed, prototyped, and evaluated LCD integrated with a gate driver and a source driver using amorphous In-Ga-Zn-Oxide TFTs having bottom-gate bottom-contact structure, thereby obtaining TFTs with superior characteristics Then, we prototyped the world's first 4-inch QVGA LCD and integrated the gate driver and source driver on the display panel

Closed-Loop Gate Drive for High Power IGBTs

Abstract: To overcome the drawbacks of the conventional gate drive, in this paper a closed-loop gate control method is proposed. In this novel method, the switching speed, specifically di/dt, is measured from the voltage across the parasitic inductance of the IGBT module and a closed-loop control is employed to adaptively adjust the gate drive voltage to control the switching speed according to a preset control reference. As a result, both the voltage overshoot and current overshoot can be effectively controlled. This new gate drive method enables programmable control of switching speed and allows full use of the capability of the power devices. The oscillations during IGBT switching are also reduced and associated EMI problems can be mitigated. The relationships between the controlled voltage overshoot, current overshoot and associated energy losses are derived and can provide guidelines for practical design. Also, the proposed gate drive fully utilizes gate drive signal information of amplitude and duty cycle, and provides a new capability for the system modulator to effectively control both the power electronic circuit's steady-state and transient behaviors simultaneously.

Predictive Direct Control Applied to AC Drives and Active Power Filter

Abstract: This paper presents different applications of a method called direct control. The previously developed approach has been redefined into a generalized form. The method relies on the prediction of either current or flux in discrete-time intervals and, consequently, selects the inverter voltage vector that produces the fastest possible transient. Depending on the task, two possible variants have been developed, offering a compromise between ripple in the controlled variable and switching frequency. A special effort has been made to overcome problems due to various delays (processing time, acquisition, gate driver delay, etc.) in the prediction routine, thus achieving maximum performance. The approach has been upgraded for application in AC drives, which allows additional torque control. The functional versatility of the approach has been demonstrated on different applications of power electronics (active power filter, induction machine, surface-mounted permanent-magnet synchronous machine). All applications have been tested on different laboratory models and have confirmed the validity of the approach.

Thin film transistor with two gate electrodes

Abstract: As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.

Liquid crystal display and driving method thereof

Abstract: A liquid crystal display includes a gate driver, a control circuit and a charge-sharing circuit. The control circuit provides a charge-sharing signal according to the parasitic capacitances at a first output end and a second output end in the gate driver. The charge-sharing circuit generates a third clock signal and a fourth clock signal by performing charge-sharing on a first clock signal and a second clock signal according to the charge-sharing signal. The third clock signal includes a signal falling edge which descends from a high level to a first level, and the fourth clock signal includes a signal falling edge which descends from the high level to a second level. The gate driver outputs a first gate driving signal and a second gate driving signal respectively at the first and the second output end according the third or the fourth clock signal.

High-temperature silicon carbide and silicon on insulator based integrated power modules

Abstract: This paper presents the challenges and results of fabricating a high temperature silicon carbide based integrated power module. The gate driver for the module was integrated into the power package and is rated for an ambient temperature of 250 °C. The power module was tested up to 300 V bus voltage, 160 A peak current, and 250 °C junction temperature.

Characterization of a new 4.5 kV press pack SPT+ IGBT for medium voltage converters

Abstract: Recently developed IGBT press pack devices have become a competition for IGCTs in high power industrial applications. This paper presents an overview of state-of-the-art medium voltage power semiconductors with active turn-off capability. A new 85 mm, 4.5 kV, 1.2 kA press pack SPT+ IGBT and the corresponding freewheeling diode are characterized at hard switching as a function of the parameters dc-link voltage, load current, junction temperature, stray inductance and gate unit conditions.

High-Voltage Auxiliary Power Supply Using Series-Connected MOSFETs and Floating Self-Driving Technique

Abstract: This paper deals with high-voltage auxiliary switching-mode power supplies (SMPSs) An overview of the state of the art is given, and a novel solution is proposed The proposed solution is based on a single-ended flyback or forward topology with the main switch arranged as a series connection of two metal-oxide-semiconductor field-effect transistors (MOSFETs) The bottom MOSFET is driven directly by an ordinary control circuit and gate driver, while the top MOSFET is driven by a floating self-supplied gate driver The floating gate driver is connected to the input filter capacitors' midpoint This gate driver plays two roles: driving of the top MOSFET and control of distribution of the blocking voltage among the series-connected MOSFETs, in steady state as well as during commutation The series connection of lower voltage MOSFETs has two important advantages compared to that of a single high-voltage MOSFET: lower conduction losses and lower cost When several switches are series connected, each switch supports a fraction of the total blocking voltage, and therefore, each switch can be rated for lower voltage The total on-state resistance and the cost of such a switch arrangement are lower compared to that of a single switch that supports the full blocking voltage The proposed SMPS is theoretically analyzed and experimentally verified The experimental results are presented and discussed

Shift register and gate driver therefor

Abstract: The present invention relates to a shift register and a gate driver therefor. The shift register comprises: a first thin film transistor, of which a gate is connected to a first node, a source is connected to a clock signal terminal, and a drain is connected to an output terminal at current stage; a second thin film transistor, of which a gate is connected to a second node, a source is connected to the output terminal at current stage, and a drain is connected to a low level signal terminal; a third thin film transistor, of which a gate is connected to the first node, a source is connected to the low level signal terminal, and a drain is connected to the second node; a fourth thin film transistor, of which a gate is connected to the second node, a source is connected to the low level signal terminal, and a drain is connected to the first node; a first capacitor connected between the clock signal terminal and the second node; a discharging module connected between the clock signal terminal and the output terminal at current stage; a compensation module connected between the first node and the low level signal terminal. The present invention has the advantages of low cost, low power consumption and long life span etc, as well as the features of high stability, strong anti-interference capability and small delay etc.

A Stepped Oxide Hetero-Material Gate Trench Power MOSFET for Improved Performance

Abstract: In this brief, we propose a new stepped oxide hetero-material trench power MOSFET with three sections in the trench gate (an N+ poly gate sandwiched between two P+ poly gates) and having different gate oxide thicknesses (increasing from source side to drain side). The different gate oxide thickness serves the purpose of simultaneously achieving the following: 1) a good gate control on the channel charge and 2) a lesser gate-to-drain capacitance. As a result, we obtain higher transconductance as well as reduced switching delays, making the proposed device suitable for both RF amplification and high-speed switching applications. In addition, the sandwiched gate with different work-function gate materials modifies the electric field profile in the channel, resulting in an improved breakdown voltage. By using 2-D simulations, we have shown that the proposed device structure exhibits about 32% enhancement in breakdown voltage, 25% reduction in switching delays, 20% enhancement in peak transconductance, and 10% reduction in figure of merit (product of ON-resistance and gate charge) as compared to the conventional trench-gate MOSFET.

System and method for providing switching to power regulators

Abstract: System and method for providing switching to power regulators. According to an embodiment, the present invention provides system for providing switching. The system includes a first voltage supply that is configured to provide a first voltage. The system also includes a second voltage supply that is configured to provide a second voltage. The second voltage being independent from the first voltage. The system additionally includes a controller component that is electrically coupled to the first voltage supply. For example, the controller component being configured to receive at least a first input signal and to provide at least a first output signal. Additionally, the system includes a gate driver component that is electrically coupled to the second voltage supply. The gate driver component is configured to receive at least the first output signal and generated a second output signal in response to at least the second voltage and the first output signal.

Microcontroller based sinusoidal PWM inverter for photovoltaic application

Abstract: This paper represents the microcontroller based sinusoidal PWM inverter for photovoltaic application. The advantage of this inverter is the use of a low cost microcontroller that has built in PWM modules. Microcontroller PIC 18F4431 is able to store the required commands to generate the necessary PWM waveforms. The required dead time has been implemented low cost. The application of this inverter is to be either for stand-alone or for grid connected from a direct supply of photovoltaic (PV) Cells. In this paper how SPWM signal is generated by microcontroller and what are the features of described microcontroller is reviewed. Subsequently hardware configuration of the microcontroller, algorithm, flowchart, gate driver and isolation system are discussed. Finally the experimental results are shown in this paper.

Method and apparatus for signal inversion in superconducting logic gates

Abstract: one embodiment, the disclosure relates to a single-flux quantum logic gate capable of providing output from one of the two inputs, which is also known as the A and NOT B gate. The logic gate includes a first input gate and a second input gate for respectively receiving a first input pulse and a second input pulse. An output gate is wired in parallel with the first input gate. A first Josephson junction and a second Josephson junction are connected to the first input gate and the second input gate, respectively. A cross-coupled transformer is also provided. The cross-coupled transformer diverts the first pulse from the output gate if the second pulse is detected at the second input gate. In an optional embodiment, the first Josephson junction has a first critical current which is selected to be less than the critical current of the second Josephson junction.

Double-stage gate drive circuit for parallel connected IGBT modules

Abstract: Solid state modulators are increasingly being used in pulsed power applications. In these applications IGBT modules must often be connected in parallel due to their limited power capacity. In a previous paper, we introduced a control method for balancing the currents in the IGBTs. In this paper, we investigate techniques to minimize the modules' rise and fall times, which can positively impact the modulator's output pulse parameters, which in turn must meet the application's specifications. Further, a reduction in rise and fall times lowers switching losses and thus increases the modulator's efficiency. To reduce the voltage rise time of the pulse without increasing the maximal over-voltage of the parallel IGBTs we have investigated a double-stage gate driver with protection circuits to avoid over-voltages and over-currents. Additionally voltage edge detection has been implemented to improve current balancing. Our measurement results reveal the dependency of the rise-time and turnoff losses on the design parameters of the gate drive. We show that our design achieves a 62% reduction in the turn-off rise time, and a 32% reduction in the turn-off losses.

High-Frequency Switching of SiC High-Voltage LJFET

Abstract: In this paper, inductive-load switching of a high-voltage lateral JFET (HV-LJFET) on 4H-SiC is investigated with a monolithically integrated driver and with an external driver for high-frequency, high-temperature applications. A new ldquocapacitor-coupledrdquo gate driver circuitry is proposed and optimized to utilize a standard MOS driver and enable fast switching speed without the need for a negative power supply. Switching times and losses of the silicon carbide (SiC) HV-LJFET are characterized under various driver conditions and device temperatures. The results reveal that the temperature-independent, high switching speed of the SiC LJFET makes it possible to hard-switch at 3 MHz, 200 V, 1.2 A, and 250degC with good efficiency, significantly higher than silicon devices with similar voltage ratings.

An improved Doherty amplifier using cascaded digital predistortion and digital gate voltage enhancement

Abstract: This paper describes algorithms used to improve linearity, efficiency, and peak power of a Doherty amplifier whose auxiliary transistor gate voltage is adjusted digitally as a function of the signal envelope. Two predistortion stages are used to compensate for high-order memoryless nonlinearities and low-order memory effects. The digital gate voltage waveform is a sigmoid function of the predistorted signal's envelope with two voltage limits corresponding to class C and AB bias levels. The instantaneous gate voltage is controlled by two adjustable parameters: a breakpoint and a slope. The parameters are adjusted to reduce the variance of the AM-AM curve of the power amplifier. The enhancement of the gate voltage at higher signal envelope levels increases the peak power and improves the efficiency of the Doherty amplifier structure.

Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation

Abstract: We propose an analytical closed-form gate-interconnect interdependent delay model that accounts for the dynamic behavior of signal slope across different regions of operation. In the presence of interconnects, the gate driver influences the input slope of the driven wire affecting the interconnect delay, and the driven wire acts as a parasitic load to the driver affecting the gate delay. Hence, it is essential to consider their interdependence for an accurate estimation of the circuit delay. The proposed model converts a signal slope into its effective fan-out for a simple yet accurate delay estimation. Simulations show that, for ISCAS benchmark circuits, our framework exhibits an error of < 5.3% at each stage and < 4.3% for the path delay with a speedup of three orders of magnitude over HSPICE at the 130-nm technology node. Two test chips have been fabricated in 90- and 65-nm CMOS technologies to verify the effectiveness of the proposed model. Measured results show that, for a wide range of interconnect lengths (2000 and 1400 mum ) and geometries, the proposed model predicts the circuit delay with an error of 5.7% at a supply voltage of Vdd=1.2 V and 4.8% at Vdd=0.3 V .

Technique to improve dropout in low-dropout regulators by drive adjustment

Abstract: An electronic device includes a low drop-out regulator for providing a regulated output voltage. The low drop-out regulator generally comprises a power MOSFET transistor having a gate coupled to a driver. The driver has a first path including an NMOS transistor and being coupled to the gate of the power MOSFET, a second path having a PMOS transistor and being coupled to the gate of the power MOSFET, and a switch for alternately switching between the first and second paths so as to provide a voltage to the gate of the power MOSFET ranging from ground to a power supply level.

Pull-In and Release Voltage Design for Nanoelectromechanical Field-Effect Transistors

Abstract: The Euler-Bernoulli beam equation is solved simultaneously with the Poisson equation in order to accurately model the switching behavior of nanoelectromechanical field-effect transistors (NEMFETs). Using this approach, the shape of the movable gate electrode and semiconductor potential across the width of the channel are derived for the various regimes of transistor operation (before gate pull-in, after gate pull-in, and at the point of gate release). The impact of various transistor design parameters such as the body doping concentration, gate work function, gate stiffness, and as-fabricated actuation gap thickness, as well as source-to-body bias voltage and surface forces, on the gate pull-in and gate release voltages are examined. A unified pull-in/release voltage model is developed to facilitate NEMFET design for digital- and analog-circuit applications.

Non-volatile memory with reduced leakage current for unselected blocks and method for operating same

Abstract: A memory device with reduced leakage current during programming and sense operations, and a method for operating such a memory device. In a non-volatile memory device, current leakage at the drain select gates of NAND strings can occur in unselected blocks when a selected block undergoes a program or read operation, and the bit lines are shared by the blocks. In one approach, in which a common transfer gate driver is provided for both blocks, the drain select gates are pre-charged at an optimum level, which minimizes leakage, and subsequently floated while a program or read voltage is applied to a selected word line in the selected block. In another approach, a separate transfer gate driver is provided for the unselected block so that the optimal select gate voltage can be driven in the unselected block, even while the program or read voltage is applied in the selected block.

Current-source gate driver

Abstract: Provided is a current-source gate driver for use with a switching device having a gate capacitance, including an input terminal for receiving a DC voltage; a first switch connected between the input terminal and an output terminal; a second switch connected between the output terminal and a circuit common; a series circuit comprising a first capacitor and an inductor, the series circuit connected between the input terminal and the output terminal; wherein the gate capacitance of the switching device is connected between the output terminal and the circuit common. The current-source gate driver improves efficiency of the power switching devices of a voltage regulator module or other switching converter.

Half-bridge LLC resonant converter with self-driven synchronous rectifiers

Abstract: The present invention discloses a half-bridge LLC resonant converter with self-driven synchronous rectifiers, which utilizes a primary IC controller and a gate driver to drive the secondary synchronous rectifiers. In correspondence with the gate drive output voltages of the primary IC controller to the primary switch transistors, the gate driver for the secondary synchronous rectifiers comprises a differential transformer if the primary IC controller outputs two ground-referenced gate drive voltages, which cannot directly drive the primary switch transistors but can be imposed on the differential transformer; or comprises a DC shifter, a DC restorer and a differential transformer if the primary IC controller outputs two gate-source voltages, which can directly drive the primary switch transistors but cannot be imposed on the differential transformer. The drive voltages of the primary switch transistors are unipolar; however the drive voltage of the secondary synchronous rectifiers can be bipolar or unipolar. Under the valid operation mode, this converter can decrease the rectifier conduction losses to increase the power converter efficiency.

A Cost-Effective Solution to Power the Gate Drivers of Multilevel Inverters using the Bootstrap Power Supply Technique

Abstract: Multilevel inverters are traditionally seen as a step forward in DC/AC conversion, providing more output voltage levels, better quality of the generated waveform and lower switching losses than the two-level and can process higher voltages with a given forced commutated switch technology. There are also drawbacks associated with this technology: more switching devices and associated gate driver circuitry, more complex modulation and control of the DC-link capacitor voltage sharing etc, which as of now limit its application to the high voltage/power range. This paper proposes a cost-effective solution to implement the power supply needed for powering the gate drivers based on the bootstrap supply technology, which will not need isolated DC/DC supplies for each gate driver, reducing the overall cost of a multilevel assembly and making it more appealing for lower power applications.

Liquid crystal display having function of eliminating power-off ghost shadow

Abstract: The invention relates to a liquid crystal display having a function of eliminating power-off ghost shadow The liquid crystal display comprises a display panel, a power supply device, a source driver and a gate driver The source driver comprises a hysteresis function comparator and a level conversion unit The hysteresis function comparator is used for comparing a power supply voltage supplied by the power supply device with a reference voltage The level conversion unit is coupled with the output end of the hysteresis function comparator and is used for generating a control signal The gate driver turns on a plurality of scanning lines of the display panel according to the control signal

Touch type electrophoretic display device

Abstract: A touch type electrophoretic display device includes: a first substrate on which a plurality of gate lines and a plurality of data lines cross to define a plurality of pixels; a plurality of sensing signal lines formed to be parallel to the data lines on the first substrate; a plurality of first touch driving voltage lines formed to be parallel to the gate lines; a driving thin film transistor (TFT) formed at each pixel so as to be connected to the gate lines and the data lines; a pixel electrode formed at each pixel so as to be connected to the driving TFT; a switching TFT formed at each pixel so as to be connected to the sensing signal lines and the gate lines; a lo photo TFT formed in each pixel so as to be connected to the first touch driving voltage lines and the switching TFT and serving to recognize an applied touch; a second substrate attached to the first substrate in a facing manner; a common electrode formed on the second substrate; an electrophoretic film formed between the first and second substrates; a lead-out driver for detecting a position of the photo TFT when a sensing signal is transferred via the switching TFT in a corresponding pixel and the sensing signal lines according to an operation of the photo TFT, and outputting touch data; a gate control signal generating unit for outputting a second gate control signal indicating a touch mode operation when touch data is not inputted from the lead-out driver, and outputting a first gate control signal indicating a driving mode operation for converting an image if it is determined that a touch has been applied upon receiving touch data from the lead-out driver; and a gate driver for driving the gate lines upon receiving the first or second gate control signal from the gate control signal generating unit, wherein a timing at which each gate line is turned on and off when the gate driver receives the first gate control signal and a timing at which each gate line is turned on and off when the second gate control signal is received are different.

Method of driving a gate line, gate drive circuit for performing the method and display apparatus having the gate drive circuit

Abstract: There is provided a method of driving a gate line, a gate drive circuit for performing the method, and a display apparatus having the gate drive circuit. In the method, a plurality of gate signals, generated from a plurality of shift registers connected to a plurality of gate lines, is applied to the gate lines. An output of the gate signals is blocked during a vertical blanking interval, and then a gate off voltage is applied to the gate lines. Therefore, an output signal of the gate drive circuit may maintain a gate off voltage during a vertical blanking interval in which a clock signal is not applied to a gate drive circuit.

Gate Drive Circuit, Display Device Having the Same and Method of Manufacturing the Gate Drive Circuit

Abstract: A gate drive circuit includes a shift register having stages connected to each other in series. An (m)-th stage (‘m’ is a natural number) includes an output part, a discharging part, a first holding part and a second holding part. The output part outputs the first clock signal as a gate signal in response to a first clock signal provided from an external device and discharges the gate signal in response to a second input signal. The output part includes a first transistor having a first channel length. The discharging part discharges a signal of the first node to the second voltage level. The first holding part maintains a signal of the first node at a level of the gate signal, and is discharged to the second voltage level. The first holding part includes a second transistor having a second channel length that is longer than the first channel length. The second holding part maintains a signal of the first node at a level of the second voltage level.

A Low-Consumption Regulated Gate Driver for Power MOSFET

Abstract: Driving power MOSFET at high switching frequency may induce significant switching power losses. A gate driver with low energy consumption is proposed for power MOSFET in switching power conversion applications. The proposed gate driver regulates the output gate driving voltage for minimizing the loss of charging and discharging the gate capacitor. No extra off-chip components are required, and hence, the proposed approach can be completely designed on chip. A 40 V/0.5 mum CMOS technology is utilized and experiments on a boost converter are performed. The power dissipation of the proposed gate driver, compared with the conventional gate driver, can be reduced up to 15.5% and 55.4% under 15 V and 30 V supply voltage, respectively.