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Showing papers on "Gate driver published in 2011"


Journal ArticleDOI
TL;DR: In this article, the authors implemented a high-performance amorphous-indium-gallium-zincoxide thin-film transistors (TFTs) on polyimide/polyethylene-terephthalate plastic substrates.
Abstract: Circuits implemented with high-performance amorphous-indium-gallium-zinc-oxide thin-film transistors (TFTs) are realized on polyimide/polyethylene-terephthalate plastic substrates. The TFTs on plastic exhibit a saturation mobility of 19 cm2/V·s and a gate voltage swing of ~0.14 V/dec. For an input of 20 V, an 11-stage ring oscillator operates at 94.8 kHz with a propagation delay time of 0.48 μs. A shift register, consisting of ten TFTs and one capacitor, operates well with good bias stability. AC driving of pull-down TFTs gives the gate driver an improved lifetime of over ten years.

180 citations


Patent
06 Sep 2011
TL;DR: In this paper, a display device with touch sensors and a method of driving the same is described, which includes a display panel (10) including a pixel array including pixels and a touch sensor array including touch sensors (TS) formed in the pixel array.
Abstract: A display device having touch sensors and a method of driving the same are disclosed. The display device includes a display panel (10) including a pixel array including pixels and a touch sensor array including touch sensors (TS) formed in the pixel array, the pixel array being divided into blocks and driven, a gate driver (14) to sequentially drive a plurality of gate lines in the pixel array in a block unit, a data driver (12) to drive a plurality of data lines in the pixel array whenever the gate lines are driven, a touch controller (20) to sequentially drive the touch sensor arrays in the block unit, and a timing controller (16) to divide one frame into at least one display mode at which the pixel array is driven and at least one touch sensing mode at which the touch sensor array is driven and to control the gate driver (14), the data driver (12) and the touch controller (20) so that the display mode and the touch sensing mode alternate.

147 citations


Proceedings ArticleDOI
06 Mar 2011
TL;DR: In this article, an air-cooled inverter system for 120 °C ambient temperature is presented, where the operation of the signal electronics and the gate driver for power semiconductors with a junction temperature of 250 °C within the specified operating temperature range is ensured by appropriate placement and cooling methods, while taking the electrical requirements for limits on the wiring inductances and symmetry requirements into account.
Abstract: The degree of integration of power electronic converters in current hybrid electric vehicles can be increased by mitigation of special requirements of these converters, especially those regarding ambient air and cooling fluid temperature levels. Today, converters have their own cooling circuit or are placed far away from hot spots caused by the internal combustion engine and its peripheral components. In this paper, it is shown, how the use of SiC power semiconductors and active control electronics cooling employing a Peltier cooler can help to build an air-cooled inverter system for 120 °C ambient temperature. First, a detailed analysis shows, how the optimum junction of this high-temperature system can be calculated. Then, the operating temperature ranges of power semiconductors, thermal interface materials, capacitors, and control electronics are investigated, leading to a comprehensive analysis of mechanical concepts for the inverter system in order to show new ways to solve electrical and thermal tradeoffs. In particular, the operation of the signal electronics and the gate driver for power semiconductors with a junction temperature of 250 °C within the specified operating temperature range is ensured by appropriate placement and cooling methods, while taking the electrical requirements for limits on the wiring inductances and symmetry requirements into account. The analysis includes an accurate thermal model of the converter and an optimized active cooling of the signal electronics using a Peltier cooler. Finally, a hardware prototype with discrete power semiconductor devices and thus with a junction temperature limit of 175 °C driving high-speed electrical machines is shown to validate the theoretical considerations in a custom-designed high-temperature test environment.

127 citations


Proceedings ArticleDOI
06 Mar 2011
TL;DR: In this article, the design and hardware implementation and testing of 20kVA Gen-1 silicon based solid state transformer (SST), the high input voltage and high voltage isolation requirement are two major concerns for the SST design.
Abstract: This paper presents the design and hardware implementation and testing of 20kVA Gen-1 silicon based solid state transformer (SST), the high input voltage and high voltage isolation requirement are two major concerns for the SST design. So a 6.5kV 25A dual IGBT module has been customized packaged specially for this high voltage low current application, and an optically coupled high voltage sensor and IGBT gate driver has been designed in order to fulfill the high voltage isolation requirement. This paper also discusses the auxiliary power supply structure and thermal management for the SST power stage.

81 citations


Proceedings ArticleDOI
06 Mar 2011
TL;DR: In this article, a bidirectional solid-state circuit breakers (BDSSCBs) gate driver was developed for both self-triggered temperature-compensated overcurrent protection, and external triggering.
Abstract: Bidirectional solid-state circuit breakers (BDSSCBs) can replace mechanical fault protection devices in systems having bidirectional current flow through a single bus, for increased transition speed, functionality, and reliability. Silicon carbide, 1200-V, 0.1-cm2 JFETs were designed and fabricated for the BDSSCB application. A novel BDSSCB gate driver was developed for both self-triggered temperature-compensated over-current protection, and external triggering. Bidirectional 600-V, 60-A fault isolation was demonstrated in a transition time of approximately 10 μs with two packaged JFET modules, a bidirectional RCD snubber, and a series distribution bus inductance of 20 μH.

75 citations


Proceedings ArticleDOI
06 Mar 2011
TL;DR: In this article, the static and dynamic characteristics of single discrete silicon carbide (SiC) JFET and BJT devices were obtained over a wide range of temperature to study the scaling of device parameters.
Abstract: This paper presents an analysis of single discrete silicon carbide (SiC) JFET and BJT devices and their parallel operation. The static and dynamic characteristics of the devices were obtained over a wide range of temperature to study the scaling of device parameters. The static parameters like on-resistance, threshold voltage, current gains, transconductance, and leakage currents were extracted to show how these parameters would scale as the devices are paralleled. A detailed analysis of the dynamic current sharing between the paralleled devices during the switching transients and energy losses at different voltages and currents is also presented. The effect of the gate driver on the device transient behavior of the paralleled devices was studied, and it was shown that faster switching speeds of the devices could cause mismatches in current shared during transients.

73 citations


Patent
Yikui Jen Dong1
22 Dec 2011
TL;DR: In this paper, a differential line driver with N-paralleled slices for driving an impedance-matched transmission line is presented, where each transistor in each driver slice has a resistor disposed between the transistor and the respective output node of the driver to enhance ESD protection of the transistors.
Abstract: A differential line driver with N-paralleled slices for driving an impedance-matched transmission line. Each driver slice is a modified H-bridge driver using low-voltage, high-speed transistors. By using a voltage-dropping first resistor in each slice, a high-voltage power supply that would normally damage the transistors can be used to power the driver and produce a differential output signal with peak-to-peak amplitudes that otherwise might not be possible. Each transistor in each driver slice has a resistor disposed between the transistor and the respective output node of the driver to enhance ESD protection of the transistors and, in combination with the first resistor, to impedance match the driver to the transmission line.

70 citations


Journal ArticleDOI
TL;DR: In this article, a new dc-dc converter suitable for operation at very high frequencies (VHF) under on-off control is introduced, which is based on a resonant inverter providing low switch voltage stress and fast settling time compared to other resonant topologies.
Abstract: This paper introduces a new dc-dc converter suitable for operation at very high frequencies (VHF) under on-off control. The converter power stage is based on a resonant inverter (the Φ2 inverter) providing low switch voltage stress and fast settling time compared to other resonant topologies. A new multistage resonant gate driver suited for driving large, high-voltage RF Mosfet at VHF frequencies is also introduced. Experimental results are presented from a prototype dc-dc converter operating at 30 MHz at input voltages up to 200 V and power levels above 200 W under closed-loop control. These results demonstrate the high performance achievable with the proposed design.

69 citations


Proceedings ArticleDOI
06 Mar 2011
TL;DR: The presented topology, which consists of a class E inverter, class E rectifier, and self-oscillating gate driver, is inherently resonant, and switching losses are greatly reduced by ensuring Zero Voltage Switching of the power semiconductor devices.
Abstract: This paper describes the analysis and design of a DC-DC converter topology which is operational at frequencies in the Very High Frequency (VHF) band ranging from 30 MHz–300 MHz. The presented topology, which consists of a class E inverter, class E rectifier, and self-oscillating gate driver, is inherently resonant, and switching losses are greatly reduced by ensuring Zero Voltage Switching (ZVS) of the power semiconductor devices. A design method to ensure ZVS operation when combining the inverter, rectifier, and gate driver is provided. Several parasitic effects and their influence on converter operation are discussed, and measurement results of a 100 MHz prototype converter are presented and evaluated. The designed prototype converter verifies the described topology.

68 citations


Patent
18 Oct 2011
TL;DR: In this article, a method for using gate driver units with distributed intelligence to control antiparallel power modules or parallel-connected electrical switching devices like IGBTs is described. But the intelligent gate drive units use the intelligence to balance the currents of the switching devices, even in dynamic switching events.
Abstract: An exemplary apparatus and method for using intelligent gate driver units with distributed intelligence to control antiparallel power modules or parallel-connected electrical switching devices like IGBTs is disclosed. The intelligent gate drive units use the intelligence to balance the currents of the switching devices, even in dynamic switching events. The intelligent gate driver units can use master-slave or daisy chain control structures and instantaneous or time integral differences of the currents of parallel-connected switching devices as control parameters. Instead of balancing the currents, temperature can also be balanced with the intelligent gate driver units.

56 citations


Journal ArticleDOI
TL;DR: Based on the use of a standard five-mask process, the authors presents a new integrated hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) gate driver circuit for large size TFT-LCD applications.
Abstract: Based on the use of a standard five-mask process, this work presents a new integrated hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) gate driver circuit for large size TFT-LCD applications, composed of a pull-up circuit with three TFTs, a pull-down circuit with ten TFTs, and two capacitors. The pull-up circuit, which separates the row line from the carry signal, prevents distortion of the output pulse. Moreover, the pull-down circuit with the AC-driving method can reduce the threshold voltage shift ( shift) to stabilize the output voltage and suppress the fluctuation of the row line, subsequently increasing the operating lifetime. According to accelerated lifetime test results, this gate driver circuit operates stably over 240 hours at 100°C. Additionally, the scan direction of the proposed circuit can be modified using two control signals and applied to the reversal display of an image.

Patent
21 Sep 2011
TL;DR: In this article, a liquid crystal display (LCD) with an integrated touch screen panel includes a plurality of pixels connected to a multiplicity of data lines and gate lines, the gate lines being divided into groups, a common electrode driver configured to simultaneously supply a driving signal to common electrodes within each group of the plurality of groups of the common electrodes, and to sequentially supply the driving signals to the plurality groups of common electrodes.
Abstract: A liquid crystal display (LCD) with an integrated touch screen panel includes a plurality of pixels connected to a plurality of data lines and a plurality of gate lines, the gate lines being divided into a plurality of groups, a plurality of sensing electrodes, a plurality of common electrodes divided into a plurality of groups, a common electrode driver configured to simultaneously supply a driving signal to common electrodes within each group of the plurality of groups of the common electrodes, and to sequentially supply the driving signal to the plurality of groups of the common electrodes, and a gate driver configured to sequentially supply a gate signal to gate lines within each of the plurality of group of the gate lines

Proceedings ArticleDOI
01 Nov 2011
TL;DR: In this article, a robust control algorithm is developed to adapt the gate current waveforms to the desired switching behavior, irrespective of the operating conditions, and implemented in a Field-Programmable Gate Array (FPGA) on the gate unit and experimentally verified for several optimization objectives.
Abstract: Digital technology incorporated into the gate drive unit of HV-IGBTs allows new features, like automatic optimization of the gate current waveforms for achieving certain properties of the switching transients, or automatic adaptation to the operating conditions. This paper presents a digital gate unit with on-line measurement of the IGBT's switching waveforms. Based on this, a robust control algorithm is developed to adapt the gate current waveforms to the desired switching behavior, irrespective of the operating conditions. The algorithm is implemented in a Field-Programmable Gate Array (FPGA) on the gate unit and experimentally verified for several optimization objectives using 3.3 kV and 1200 A IGBTs.

Journal ArticleDOI
TL;DR: In this article, an inductive power link for remote powering of a wireless cortical implant is presented, which includes a Class-E power amplifier, a gate driver, inductive link, and an integrated rectifier.
Abstract: This paper presents an inductive power link for remote powering of a wireless cortical implant. The link includes a Class-E power amplifier, a gate driver, an inductive link, and an integrated rectifier. The coils of the inductive link are designed and optimized for remote powering from a distance of 10 mm (scalp thickness). The power amplifier is designed in order to allow closed-loop control of the power delivered to the implant, by controlling the supply voltage. Moreover, a gate driver is added to the system to drive the power amplifier and to characterize the gate losses. A new packaging topology is proposed in order to position the implant inside a hole in the cranial bone, without occupying a large area, but still obtaining a short distance between the remote powering coils. The package is fabricated by using biocompatible materials such as PDMS and Parylene-C. The power efficiency of the remote powering link is characterized for a wide range of load power (1-20 mW) delivered from the rectifier and is measured to be 24.6% at nominal load of 10 mW.

Proceedings ArticleDOI
01 Jun 2011
TL;DR: In this article, the static and dynamic characteristics of ultra fast silicon (Si) and SiC Schottky diodes were compared and the mechanism of parasitic high frequency oscillations during turn-off transient was studied.
Abstract: Advanced control systems combined with high speed gate driver circuits enable extremely high rate of change of power devices voltages, up to hundreds of kV/us. Short rise times of power devices could cause significant EMC problems, which are unacceptable in majority of power electronics applications. It is known that voltage variations during diode switch-off depend on how long it takes for the charge stored near the p-n junction to be recovered during voltage reversing. In fast switching applications good forward recovery characteristics are needed. The silicon carbide (SiC) diodes characterize almost zero reverse recovery charge. However the lossless operation in connection with extremely high dv/dt could cause the SiC diodes less effective in damping the voltage ringing. The compromise between high efficiency and low EMI emission is therefore the actual aim of the research. The paper compares the static and dynamic characteristics of ultra fast silicon (Si) and SiC Schottky diodes and presents the study of the mechanism of parasitic high frequency oscillations during turn-off transient.

Proceedings ArticleDOI
06 Mar 2011
TL;DR: In this paper, a high-voltage, high-temperature SOI-based gate driver for SiC FET switches is proposed for hybrid electric vehicles (HEVs).
Abstract: The growing demand for hybrid electric vehicles (HEVs) has increased the need for high-temperature electronics that can operate at the extreme temperatures that exist under the hood. This paper presents a high-voltage, high-temperature SOI-based gate driver for SiC FET switches. The gate driver is designed and implemented on a 0.8-micron BCD on SOI process. This gate driver chip is intended to drive SiC power FETs for DC-DC converters and traction drives in HEVs. To this end, the gate driver IC has been successfully tested up to 200oC. Successful operation of the circuit at this temperature with minimal or no heat sink, and without liquid cooling, will help to achieve higher power-to-volume as well as power-to-weight ratios for the power electronics modules in HEVs.

Patent
07 Jun 2011
TL;DR: In this article, a transistor is incorporated in the DC-DC converter and functions as a switching element for controlling output power, which enables the threshold voltage to decrease the on-state resistance when the output power is high and to increase the off-state current when low.
Abstract: Provided is a DC-DC converter with improved power conversion efficiency. A transistor which is incorporated in the DC-DC converter and functions as a switching element for controlling output power includes, in its channel formation region, a semiconductor material having a wide band gap and significantly small off current compared with silicon. The transistor further comprises a back gate electrode, in addition to a general gate electrode, and a back gate control circuit for controlling a potential applied to the back gate electrode in accordance with the output power from the DC-DC converter. The control of the potential applied to the back gate electrode by the back gate control circuit enables the threshold voltage to decrease the on-state resistance when the output power is high and to increase the off-state current when the output power is low.

Proceedings Article
15 Sep 2011
TL;DR: This paper presents the modularized design and analysis of a phase-leg module based on the Power Electronics Building Block (PEBB) concept, which aims at generalizing the phase-Leg as a subsystem for various converter topologies through smart control schemes.
Abstract: This paper presents the modularized design and analysis of a phase-leg module based on the Power Electronics Building Block (PEBB) concept, which aims at generalizing the phase-leg as a subsystem for various converter topologies through smart control schemes. The recently commercialized 1200 V SiC MOSFETs and SiC Schottky diodes from Cree are used as the main switches of the phase-leg, in order to explore the potentials of the pure SiC systems in achieving higher switching frequency and power density for 600 to 800 V, medium-power converters. To build the phase-leg module, the new SiC MOSFET has been fully characterized beyond the datasheet temperature range. The device switching speed has also been pushed as fast as possible through optimized gate driver and circuit layout designs, so as to achieve the high-frequency operation capability of the SiC PEBBs.

Proceedings ArticleDOI
01 Nov 2011
TL;DR: In this paper, the authors proposed a delay time compensation method for low and medium voltage converters with parallel connected IGBTs, which is a low expensive and automated delay-time compensation method without additional current measurements.
Abstract: The parallel connection of IGBTs is being applied in various low and medium voltage converters. The selection of the devices, the manual parameterization of gate units and the substantial device de-rating are substantial disadvantages of state of the art converters with parallel connected IGBTs. This paper introduces a new, low expensive and automated delay time compensation method without additional current measurements. The structure and function of the new scheme are described in detail. Finally, the performance of the new delay time compensation principle is verified by experimental investigations of two parallel connected (1700V, 450 A) IGBT modules.

Journal ArticleDOI
TL;DR: In this paper, a new integrated gate driver has been successfully designed and fabricated by amorphous silicon (a-Si) technology for a 3.8-in WVGA (800 × 480) TFT-LCD panel.
Abstract: A new integrated gate driver has been successfully designed and fabricated by amorphous silicon (a-Si) technology for a 3.8-in WVGA (800 × 480) TFT-LCD panel. With the proposed threshold voltage drop-cancellation technique, the output rise time of the proposed integrated gate driver can be substantially decreased by 24.6% for high-resolution display application. Moreover, the proposed noise reduction path between the adjacent gate drivers can reduce the layout area for slim bezel display. The transmittance brightness and contrast ratio of the demonstrated 3.8-inch panel show almost no degradation after the 500 h operation under 70°C and -20°C conditions.

Patent
Satoshi Tomioka1
07 Sep 2011
TL;DR: In this article, a bridgeless power factor correction converter (TPBL converter) is configured such that a gate driver controls the ON ratio of a booster converter switch so that the on ratio gradually increases from 0 to 1, i.e., performs soft start control.
Abstract: A bridgeless power factor correction converter is configured such that a gate driver controls the ON ratio of a booster converter switch so that the ON ratio is gradually increased from 0, i.e., performs soft start control, every time the voltage polarity of an AC input in a totem-pole bridgeless power factor converter (TPBL converter is inverted) is inverted.

Journal ArticleDOI
TL;DR: In this paper, the authors proposed a virtual junction temperature estimation method based on the real-time measurement of semiconductor's quasi-threshold voltage using dedicated modified gate driver circuit.
Abstract: Temperature management and control are among the most critical functions in power electronic devices. Knowledge of power semiconductor’s operating temperature is important for circuit design, as well as for converter control. Virtual junction temperature measurement or estimation is not an easy task, therefore designing the appropriate circuitry for virtual junction temperature in the real operating conditions not affecting regular circuit operation is a demanding task for engineers. The proposed method enables virtual junction temperature estimation based on the real-time measurement of semiconductor’s quasi-threshold voltage using dedicated modified gate driver circuit.

Proceedings ArticleDOI
07 Jul 2011
TL;DR: In this paper, a SiC JFET based, 200 °C, 50 kW three-phase inverter module is presented, where each switching element is composed of four paralleled SiC jFETs (1200 V/25 A each) and two anti-parallel SiC Shottky Barrier Diodes (SBDs).
Abstract: Research on silicon carbide (SiC) power electronics has shown their advantages in high temperature and high efficiency applications. This paper presents a SiC JFET based, 200 °C, 50 kW three-phase inverter module and evaluates its electrical performance. With 1200 V, 100 A rating of the module, each switching element is composed of four paralleled SiC JFETs (1200 V/25 A each) and two anti-parallel SiC Shottky Barrier Diodes (SBDs). The substrate layout inside the module is designed to reduce package parasitics. Then, experimental static characteristics of the module are obtained over a wide range of temperature, and low on-state resistance is shown up to 200 °C. A gate driver, with different turn-on, turn-off gate resistances and RCD network, is designed to optimize the switching performances. The module is verified to have low power loss, fast switching characteristics at 650 V dc bus voltage, 60 A drain current, in both simulation and experiments. Finally, switching time and losses, obtained from simulation and experiment, are compared.

Journal ArticleDOI
TL;DR: In this article, the effects of parasitic capacitances in the series connection of insulated-gate bipolar transistors (IGBTs) on their voltage sharing were analyzed and two solutions were proposed to minimize these effects in order to achieve a better voltage balancing.
Abstract: This paper analyzes the effects of parasitic capacitances in the series connection of insulated-gate bipolar transistors (IGBTs) on their voltage sharing. These parasitics exist naturally due to gate driver interconnects and power circuit physical architecture. Two solutions, which can be combined, are proposed to minimize these effects in order to achieve a better voltage balancing. The first one is based on gate driver self-powering technique. The second one is based on a vertical structure assembly of IGBTs connected in series. The performance offered by these two complementary solutions is investigated and validated on a series connection of three IGBTs in a chopper converter. Both simulation and experimental results show the effectiveness of our approaches.

Patent
Wen Fa Hsu1, Chi Mao Hung1
15 Apr 2011
TL;DR: In this paper, the pulse adjustment circuit adjusts the plurality of pulses of the power signals or selects the appropriate voltage levels for the power signal to have cutting angles or enlarged amplitudes, whereby the influence of the feedthrough voltage on the thin film transistors of the driving circuit would be reduced so that the display quality of the liquid crystal display is improved.
Abstract: A liquid crystal display comprises a power supply, a pulse adjustment circuit, and a gate driver. The pulse adjustment circuit is connected between the power supply and the gate driver. The power supply provides power signals. The pulse adjustment circuit adjusts the plurality of pulses of the power signals or selects the appropriate voltage levels for the power signals to have cutting angles or enlarged amplitudes, whereby the influence of the feedthrough voltage on the thin film transistors of the driving circuit would be reduced so that the display quality of the liquid crystal display is improved.

Proceedings ArticleDOI
01 Nov 2011
TL;DR: In this article, a resonant gate drive circuit is proposed to reduce the power loss associated with high frequency switching of power IGBT/MOSFETs, which is compared with traditional gate drive circuits from power consumption and switching speed points of view.
Abstract: Gallium Nitride (GaN) and Silicon Carbide (SiC) devices have been found to withstand high voltages without showing degradation [1] and can be switched at high frequencies making them attractive for high power drives. Though GaN/SiC devices can be operated at high temperature and high frequencies, it is important to develop gate drive circuits to turn ON and OFF these devices efficiently at high speeds. This paper proposes a resonant gate drive circuit that aims at reducing the power loss associated with high frequency switching of power IGBT/MOSFETs. The proposed circuit is compared with traditional gate drive circuits from power consumption and switching speed points of view. Experimental results are given to illustrate the concept.

Journal ArticleDOI
TL;DR: In this article, the authors describe the design of a compact and highly repetitive pulsed power modulator based on semiconductor switches, which has two main parts: an IGBT stack that hasa gate drive circuit for the pulse output with a variable pulse width and repetition rate, and a capacitor charger that has a controllable output voltage.
Abstract: This paper describes the design of a compact and highly repetitive pulsed power modulator based on semiconductor switches. Output specifications of the proposed modulator are as follows: variable output pulse voltage, 1-10 kV; width, 1-10 μs; pulse repetition rate (PRR), 1-50,000 pps; and average output power, 10 kW. The proposed solid-state pulsed power modulator has two main parts: an IGBT stack that hasa gate drive circuit for the pulse output with a variable pulse width and repetition rate, and a capacitor charger that has a controllable output voltage. To connect all the storage capacitors in a series for high voltage pulses, a simple and reliable IGBT stack structure was proposed based on the Marx generator. In addition, the gate driver circuit, which supplies power and signals to all the IGBTs simultaneously, was introduced. This providesa superior protection function against the arc and the short. To charge the storage capacitors, a novel 10 kW (10 kV, 1 A) high voltage capacitor charger with the combined advantage of a series-loaded resonant converter and a ZVS (zero-voltage-switching) full-bridge pulse width modulation (PWM) converter was proposed and designed especially for the solid-state pulsed power modulator. Theexperiment results verified that the proposed scheme and structure can be used effectively for a high voltage pulsed power modulator that requires variable voltage, repetition rate, and pulse width, depending on the process of the applications.

Patent
29 Apr 2011
TL;DR: In this article, a switching gate driver of an IGBT device, including a resistor unit to control a gate current of the IGBT, and a voltage reader that outputs a control signal to control the variable resistor unit of the resistor unit.
Abstract: Disclosed is a switching gate driver of an IGBT device, including a resistor unit to control a gate current of the IGBT device; and a voltage reader that outputs a control signal to control a variable resistor unit of the resistor unit to the resistor unit, according to a collector-emitter voltage of the IGBT device.

Patent
30 Mar 2011
TL;DR: In this article, the authors describe a liquid crystal display with a timing controller that includes a gate control signal generator controlling the gate driver, a data controller controlling the data driver, and a vertical enable signal generator generating a vertical-enable signal according to the data enable signal.
Abstract: A liquid crystal display device includes a liquid crystal panel, gate and data drivers providing the liquid crystal panel with gate and data signals, and a timing controller receiving input signals that include an image signal, a sync signal, a data enable signal and a clock signal, wherein the timing controller includes a gate control signal generator controlling the gate driver, a data control signal generator controlling the data driver, a data processor supplying the image signal to the data driver, and a vertical enable signal generator generating a vertical enable signal according to the data enable signal and controlling the gate control signal generator and the data control signal generator.

Proceedings ArticleDOI
01 Nov 2011
TL;DR: Several strategies are implemented to improve the phase-leg gate drive performance and alleviate the cross-talking issue and an improved edge triggered gate drive topology is proposed.
Abstract: In order to take full advantage of the SiC devices' high-temperature and high-frequency capabilities, a transformer isolated gate driver is designed for the SiC JFET phase leg module to achieve a fast switching speed of 26V/ns and a small cross-talking voltage of 4.2V in a 650V and 5A inductive load test. Transformer isolated gate drive circuits suitable for high-temperature applications are compared with respect to different criteria. Based on the comparison, an improved edge triggered gate drive topology is proposed. Then, using the proposed gate drive topology, special issues in the phase-leg gate drive design are discussed. Several strategies are implemented to improve the phase-leg gate drive performance and alleviate the cross-talking issue. Simulation and experimental results are given for verification purposes.