Showing papers on "Gate driver published in 2017"
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TL;DR: An overview on the history of the development of insulated gate bipolar transistors (IGBTs) as one key component in today's power electronic systems is given; the state-of-the-art device concepts are explained as well as an detailed outlook about ongoing and foreseeable development steps is shown as discussed by the authors.
Abstract: An overview on the history of the development of insulated gate bipolar transistors (IGBTs) as one key component in today’s power electronic systems is given; the state-of-the-art device concepts are explained as well as an detailed outlook about ongoing and foreseeable development steps is shown. All these measures will result on the one hand in ongoing power density and efficiency increase as important contributors for worldwide energy saving and environmental protection efforts. On the other hand, the exciting competition of more maturing Si IGBT technology with the wide bandgap successors of GaN and SiC switches will go on.
201 citations
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TL;DR: In this article, a condition monitoring method of insulated-gate bipolar transistor (IGBT) modules is proposed to improve the reliability of power electronic systems to comply with more stringent constraints on safety, cost, and availability.
Abstract: Power electronic systems have gradually gained an important status in a wide range of industrial applications such as renewable generation, motor drives, automotive, and railway transportation. Accordingly, recent research makes an effort to improve the reliability of power electronic systems to comply with more stringent constraints on safety, cost, and availability. The power devices are one of the most reliability-critical components in power electronic systems. Therefore, its condition monitoring plays an important role to improve the reliability of power electronic systems. This paper proposes a condition monitoring method of insulated-gate bipolar transistor (IGBT) modules. In the first section of this paper, a structure of a conventional IGBT module and a related parameter for the condition monitoring are explained. Then, a proposed real-time on-state collector–emitter voltage measurement circuit and condition monitoring strategies under different operating conditions are described. Finally, experimental results confirm the feasibility and effectiveness of the proposed method.
134 citations
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TL;DR: A novel active gate driver (AGD) for improving the SiC MOSFET switching trajectory with high performance is presented and results show that the AGD can reduce the overshoots, oscillations, and losses without compromising the EMI.
Abstract: The trend in power electronic applications is to reach higher power density and higher efficiency. Currently, the wide band-gap devices such as silicon carbide MOSFET (SiC MOSFET) are of great interest because they can work at higher switching frequency with low losses. The increase of the switching speed in power devices leads to high power density systems. However, this can generate problems such as overshoots, oscillations, additional losses, and electromagnetic interference (EMI). In this paper, a novel active gate driver (AGD) for improving the SiC MOSFET switching trajectory with high performance is presented. The AGD is an open-loop control system and its principle is based on gate energy decrease with a gate resistance increment during the Miller plateau effect on gate–source voltage. The proposed AGD has been designed and validated through experimental tests for high-frequency operation. Moreover, an EMI discussion and a performance analysis were realized for the AGD. The results show that the AGD can reduce the overshoots, oscillations, and losses without compromising the EMI. In addition, the AGD can control the turn-on and turn-off transitions separately, and it is suitable for working with asymmetrical supplies required by SiC MOSFETs.
128 citations
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TL;DR: In this paper, a new precursor that can be used for online condition monitoring of power mosfet gate oxide degradation is proposed, and a theoretical model is established to describe the relationship between miller platform voltage and two types of gate oxide defects, and the precursor can be extracted without impacting system operation.
Abstract: The condition monitoring problem of power devices is significant for diagnostics and prognostics of a switched-mode power supply (SMPS) system. For power mosfet , the gate oxide degradation often occurs in various applications. However, there is no online condition monitoring method for gate oxide degradation so far. In this paper, a new precursor that can be used for online condition monitoring of power mosfet gate oxide degradation is proposed. Gate oxide degradation mechanisms and effect are summarized, and the mosfet turn-on process is analyzed. Then, a theoretical model is established to describe the relationship between miller platform voltage and two types of gate oxide defects, and miller platform voltage is identified as a new precursor. The precursor can be extracted without impacting system operation, thus online condition monitoring can be accomplished. The accelerated degradation test is carried out for power mosfet s with both high electric field and gamma irradiation methods, and the degraded devices injection and in situ monitoring of miller platform voltage are conducted on a BOOST circuit to verify the feasibility of the new precursor. Experimental results demonstrate that the new precursor can be applied to online condition monitoring of power mosfet gate oxide degradation in the SMPS system.
95 citations
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TL;DR: In this paper, a new module for multilevel inverters with reduced components is presented, which produces 25 levels using four asymmetrical DC voltage sources (two 1V DC and two 5V DC sources) and 10 semiconductor switches.
Abstract: This study presents a new module for multilevel inverters with reduced components Each module produces 25 levels using four asymmetrical DC voltage sources (two 1V DC and two 5V DC sources) and 10 semiconductor switches A significant advantage of the suggested module is its potentiality in producing voltage levels with negative polarity without any end side H-bridge inverter Therefore, switches with lower voltage ratings are used in its structure Series connection of the proposed structure leads to a modular topology which produces more voltage levels using reasonable number of switches, gate driver circuits, power diodes and less DC voltage sources These advantages are analysed by comparing this structure with other state-of-the-art topologies Selective harmonic elimination pulse width modulation (SHE-PWM) scheme is used to achieve output voltage with high quality To produce all voltage levels, two algorithms are proposed to determine DC voltage sources magnitude The accuracy of the suggested module performance in producing all voltage levels is verified by simulation and experimental results
95 citations
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TL;DR: Numerical simulations are conducted to validate the proposed new concise yet accurate switching loss model for SiC power MOSFETs and provide guidelines in designing the gate driver for ultrafast SiCPower MOSfETs.
Abstract: The reduced chip size and unipolar current conduction mechanism make silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) suitable for high-frequency power electronics applications. Modeling the switching process of the SiC power MOSFET with parasitic components is important for achieving higher efficiency and power density system design. Therefore, this paper proposes a new concise yet accurate switching loss model for SiC power MOSFETs. Addressing the limitations in experimental measurements, numerical simulations are conducted to validate the proposed model taking the output capacitance C oss discharge and charge into consideration. The role of the parasitic components in the second-order model is discussed in depth for switching losses. Furthermore, this paper also provides guidelines in designing the gate driver for ultrafast SiC power MOSFETs.
85 citations
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TL;DR: An automatic optimization by simulated annealing algorithm is introduced to fully utilize the benefit of the gate driver, and the further reduction of IC overshoot and the energy loss are achieved over the manual optimization.
Abstract: A general-purpose clocked gate driver integrated circuit (IC) to generate an arbitrary gate waveform is proposed to provide a universal platform for fine-grained gate waveform optimization handling various power transistors. The fabricated IC with a 0.18 μm Bipolar-CMOS-DMOS process has 63 P-type MOS (PMOS) and 63 N-type MOS (NMOS) driver transistors on a chip whose activation patterns are controlled by 6-bit digital signals and 40 ns time step control. In the 500 V switching measurements with a manual gate waveform optimization, the proposed gate driver reduces the IC overshoot by 25% and 41%, and the energy loss by 38% and 55% for Si-insulated-gate bipolar transistor and SiC-MOSFET, respectively, which demonstrate the feasibility of driving various power devices with the same driver. An automatic optimization by simulated annealing algorithm is introduced to fully utilize the benefit of the gate driver, and the further reduction of IC overshoot by 26% and the energy loss by 18% are achieved over the manual optimization.
81 citations
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TL;DR: An active gate driving technique is proposed, which allows inverter to operate with moderate amount of layout parasitic inductance and load parasitic capacitance and dramatically reduces switching loss of the SiC MOSFET with the help of existing parasitic elements.
Abstract: High di/dt and dv/dt of SiC MOSFET cause a considerable amount of overshoot in device voltage and current during switching transients in the presence of inverter layout parasitic inductance and load parasitic capacitance. The excessive overshoots in device voltage and current cause failure of the device. Moreover, these uncontrolled overshoots increase the switching loss in the inverter. It is difficult to reduce parasitic inductance beyond a certain point. This paper proposes an active gate driving technique, which allows inverter to operate with moderate amount of layout parasitic inductance and load parasitic capacitance. The proposed technique dramatically reduces switching loss of the SiC MOSFET with the help of existing parasitic elements. The proposed switching loss reduction technique is termed as quasi zero switching . The developed active gate driver has been tested in a double pulse test setup and a 10 kW two-level voltage source inverter driving an induction motor.
79 citations
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TL;DR: In this paper, the authors used infrared measurements to assess the measurement accuracy of the peak gate current (Iワン GPeak) method for Insulated-gate bipolar transistor (IGBT)junction temperature measurement.
Abstract: Infrared measurements are used to assess the measurement accuracy of the peak gate current (I
GPeak
) method for Insulated-gate bipolar transistor (IGBT)junction temperature measurement. Single IGBT chips with the gate pad in both the center and the edge are investigated, along with paralleled chips, as well as chips suffering partial bondwire lift-off. Results are also compared with a traditional electrical temperature measurement method: the voltage drop under low current (V
CE (low )
). In all cases, the IG
Peak
method is found to provide a temperature slightly overestimating the temperature of the gate pad. Consequently, both the gate pad position and chip temperature distribution influence whether the measurement is representative of the mean junction temperature. These results remain consistent after chips are degraded through bondwire lift-off. In a paralleled IGBT configuration with nonnegligible temperature disequilibrium between chips, the I
GPeak
method delivers a measurement based on the average temperature of the gate pads.
79 citations
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TL;DR: This paper presents a novel compact circuit combining function of gate control and voltage balancing for series-connected silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET).
Abstract: This paper presents a novel compact circuit combining function of gate control and voltage balancing for series-connected silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET) Two series-connected SiC MOSFETs with the proposed circuit only require a single standard gate driver to achieve the gate control and voltage balancing during both steady-state and switching transition Moreover, the proposed circuit is only composed of ten passive components Therefore, the proposed circuit provides a low-cost and highly reliable method to increase the blocking voltage of the SiC MOSFET The operation principles of the proposed circuit are theoretically analyzed In addition, the high-blocking-voltage device is not only required in switching-mode power supply (SMPS) but also in dc-breaker applications The proposed circuit is then modified to make it suitable to the dc-breaker applications The simulation and experimental results validate the effectiveness and superiority of the proposed circuit in both SMPS and dc-breaker applications
75 citations
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TL;DR: In this article, a method for detecting the condition of bond wires in IGBT module by identifying the short-circuit current of IGBT was presented, which is based on the fact that parasitic parameters are affected by the local damage induced by ageing over time, and these changes can be easily detected by monitoring the difference of short circuit current.
Abstract: Finding and replacing the defective insulated-gate bipolar transistor (IGBT) module timely by monitoring the ageing state of IGBT can improve the reliability of a power converter and reduce the loss caused by IGBT failure. A method for detecting the condition of bond wires in IGBT module by identifying the short-circuit current of IGBT module is presented in this paper. It is based on the fact that parasitic parameters of IGBT module are affected by the local damage induced by ageing over time, and these changes can be easily detected by monitoring the difference of short-circuit current. The study results indicate that short-circuit current of IGBT module decreases with module ageing over time, and the difference of short-circuit current caused by junction temperature is much smaller than that caused by bond wires fatigue on a specific gate driving voltage. Therefore, the IGBT module in the power converter can be diagnosed by detecting the difference of short-circuit current without considering the effects of junction temperature. Finally, a confirmatory experiment is carried out, and the correctness of the method proposed in this paper is verified.
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TL;DR: An online condition monitoring method based on short-circuit current of an IGBT module, which is a good condition indicator according to the theory analysis, and has the merits of low cost and circuit simplicity.
Abstract: Insulated-gate bipolar transistor (IGBT) modules and dc-link capacitors are important parts in the majority of power electronic converters which contribute to cost, size, and failure rate on a considerable scale. This paper presents an online condition monitoring method for both IGBT modules and dc-link capacitors of power converters based on short-circuit current of an IGBT module, which is a good condition indicator according to the theory analysis. The failure prediction of dc-Link capacitor is realized by equivalent series resistance, which can be calculated by short-circuit current and a step voltage, and the bond wires fatigue can also be identified by the short-circuit current. The proposed method is capable for detecting small changes in the failure indicators of IGBT modules and electrolytic capacitors, and its effectiveness is validated by a confirmatory experiment. The novelty of the proposed method is that the degradations of IGBT modules and capacitors can be identified simultaneously, and has the merits of low cost and circuit simplicity
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TL;DR: A hybrid active gate drive is presented for both switching loss reduction and voltage balancing of the series-connected IGBTs; thus the switching loss can be suppressed without increasing the current and voltage stresses of the power device.
Abstract: Insulated gate bipolar transistors (IGBTs) are usually connected in series to form high-voltage switches in power electronics applications. However, the series operation of IGBTs is not easy due to the unbalanced voltage sharing between them, especially during the switching transients and the tail-current period. In this paper, a hybrid active gate drive is presented for both switching loss reduction and voltage balancing of the series-connected IGBTs. Compared with the conventional gate drive, the proposed method allows dynamical adjustment of the switching speed of IGBTs; thus the switching loss can be suppressed without increasing the current and voltage stresses of the power device. For series connection, the transient voltage sharing is achieved by using an adaptive control method, while the voltage balancing during the tail-current period is optimized by a low-loss snubber circuit. The performance of the proposed hybrid active gate drive and control method has been validated by experimental results.
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TL;DR: In this article, a double-end sourced layout for multichip SiC MOSFET power module adopting conventional wire-bonded packaging technology is proposed, which provides each MOS-FET with two parallel commutation loops by incorporating a symmetrical pair of dc-bus terminals into the power module.
Abstract: This paper proposes a double-end sourced layout for multichip SiC MOSFET power module adopting conventional wire-bonded packaging technology. The unique design provides each MOSFET with two parallel commutation loops by incorporating a symmetrical pair of dc-bus terminals into the power module. This new layout provides symmetrical equivalent power loops to each paralleled MOSFET and thus enables consistent switching performances and equal dynamic current sharing for the paralleled MOSFETs. Compared to the conventional design, the proposed design reduces the equivalent power-loop stray inductance by more than 50% and achieves improved dynamic current sharing among devices. By mitigating the imbalance of the switching current, the new module design demonstrated reduced temperature differences among devices and decreased near-field radiation noise level compared to the conventional layout. These features can further help to improve the power module density by shrinking the heat sink and integrating the gate driver board with the power modules. In this paper, an analytic model has been proposed for fast prediction of the near-field radiation from the power module. Detailed design procedures and experimental validations are also included in this paper.
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TL;DR: In this article, an electromagnetic interference (EMI) model for a two-stage cascaded boost converter is presented to distinguish its noise sources, and several methods are presented for minimizing the noise sources using a ferrite bead and a modified gate driver.
Abstract: In the paper, an electromagnetic interference (EMI) model for a two-stage cascaded boost converter is presented to distinguish its noise sources. To illustrate the effects of switching speeds on EMI generation potential, the relationships between the time domain and the frequency domain with all-SiC and SiC–Si device combinations are provided. It is found that the voltage ripples and spikes at turn-OFF generate common mode (CM) noise in the high-frequency range, above the cutoff frequency determined by the short switching time of the SiC MOSFET. Several methods are presented for minimizing the noise sources using a ferrite bead and a modified gate driver. Experimental measurements of SiC switching waveforms and CM EMI taken from a 600-W prototype two-stage cascaded boost converter operating at 100 kHz are presented to validate the CM noise analysis.
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TL;DR: In this paper, an active current source gate drive (ACSD) method based on voltage controlled current source (VCCS) feedback control strategy for high-power IGBTs was proposed.
Abstract: This paper proposes an active current source gate drive (ACSD) method based on voltage controlled current source(VCCS) feedback control strategy for high-power IGBTs. Unlike the common voltage source gate drive, the proposed ACSD method provides constant drive current to charge and discharge an IGBT. With a large gate drive current, high switching speed and low switching losses can be achieved in a power converter. However, a high-current/voltage overshoot occurs. To solve this problem, a feedback current proportional to the di/dt or dv/dt signal is generated to the IGBT gate. Thus, direct control of the net gate drive current is produced. Then, the current/voltage overshoot is controlled with little sacrifice in switching time, and the switching losses are lower than that with the conventional gate drive method operating simply by gate resistance switchover. The operation principle and circuit implementation of the proposed ACSD method are presented. The experimental results from a 1200 V/800 A IGBT module verify the performance of the proposed method.
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TL;DR: A gate driver based on the magnetic coupling is proposed to ensure the gate–source voltage within the safe range, even when the positive and negative spurious pulse voltages appear.
Abstract: Silicon carbide (SiC) devices have attracted widespread attention because of their superior characteristics. However, not only the higher slew rate of drain–source voltage but also the higher slew rate of reverse recovery current can result in a more serious crosstalk problem than Si-based devices in a half-bridge application. Crosstalk suppression should be integrated into the gate driver to ensure the safe operation of SiC devices. Therefore, a specific mathematical analysis is done in this paper to figure out the crosstalk phenomenon. The limitations of the existing suppression methods are illustrated. Thus, a gate driver based on the magnetic coupling is proposed to ensure the gate–source voltage within the safe range, even when the positive and negative spurious pulse voltages appear. The proposed gate driver uses three ring transformers to insulate the control signal and driver power supply. So, it is feasible to drive a half-bridge circuit in the medium or high power applications. By saving optical couplers and isolated drive power supplies, the gate driver can realize fully galvanic isolation and generate the positive and negative gate–source driving voltage simply. The results derived from the proposed mathematical analysis and the effectiveness of the proposed driver in suppressing the spurious pulse voltage are verified by the experiments.
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26 Mar 2017
TL;DR: In this paper, an analytic model for the switching process of paralleled GaN HEMT transistors is built to analyze the effects of parasitics and device characteristics on paralleling, and the design consideration for gate driver and layout is also presented.
Abstract: Industry is adopting GaN HEMT in 10kW–100kW and higher power systems due to the ultra-fast switching capabilities of GaN. Paralleling GaN HEMT transistors is an appealing idea to further increase the power capability and reduce conduction losses of systems. The characteristics of E-mode GaN HEMT, such as positive temperature coefficient of RDS(ON) and a temperature independent threshold voltage, are very suitable for paralleling devices. However, the main challenge for parallel operation is thought to be the diverse parasitics of the power stage and gate driver circuits, which are very sensitive to the high di/dt and dv/dt during the switching process. In this paper, an analytic model for the switching process of paralleled GaN HEMT transistors is built to analyze the effects of parasitics and device characteristics on paralleling, and the design consideration for gate driver and layout is also presented. A half bridge power stage consisting of four high-side and four low-side 60 A / 650 V GaN HEMTs in parallel is designed to undertake 240 A / 400 V hard switching on and off. Double pulse testing results are presented to confirm GaN paralleling capability.
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TL;DR: In this paper, a passive balancing method was proposed to force the peak switching currents of two paralleled MOSFETs turned on/off by one gate driver to track with negligible penalty in loss.
Abstract: The peak switching currents of two paralleled MOSFETs turned on/off by one gate driver could differ significantly owing to the mismatch in threshold voltages (Vth). The passive balancing method described herein employs one inductor and one resistor per MOSFET to force the currents to track with negligible penalty in loss. Sensors, feedbacks, and knowledge of gate-related parameters (such as gate charge, polarity of Vth difference, gate impedances, etc.) are not required. The passive components are designed using an inequality involving Vth, rise time, and unbalance percentage. The mismatch in peak currents is reduced from 15% to 1% between SiC MOSFETs tested at 20 A and 300 V with 19% Vth variation.
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TL;DR: In this paper, a specific architecture for a low-side/high-side gate driver implementation for power devices running at high switching frequencies and under very high switching speeds is presented.
Abstract: This paper presents a specific architecture for a low-side/high-side gate driver implementation for power devices running at high switching frequencies and under very high switching speeds. An electromagnetic interference (EMI) optimization is done by modifying the parasitic capacitance of the propagation paths between the power and the control sides, thanks to a specific design of the circuit. Moreover, to reduce the parasitic inductances and to minimize the antenna phenomenon, the paper studies which elements of the drivers’ circuitry must be brought as close as possible to the power parts. This is important when the ambient temperature of the power device becomes critical, for instance, in automotive and aeronautic applications. Simulations and experiments validate the advantages of the proposed architecture on the conducted EMI problem.
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01 Oct 2017TL;DR: In this article, a series connection of two commercially available conventional drivers and an improved 5 V, 100 ps resolution active gate driver is introduced. But the use of low-voltage, high-speed transistors limits the output voltage range to 5 V.
Abstract: Active gate driving has been shown to provide reduced circuit losses and improved switching waveform quality in power electronic circuits. An integrated active gate driver with 150 ps resolution has previously been shown to offer the expected benefits in GaN-based converters. However, the use of low-voltage, high-speed transistors limits its output voltage range to 5 V, too low for many emerging SiC and GaN devices. This paper introduces a series connection of two commercially available conventional drivers and an improved 5 V, 100 ps resolution active driver. The first conventional driver lifts the gate voltage from the negative hold-off voltage to just below the gate threshold voltage, the active driver performs active high-resolution control around the gate threshold, after which the second conventional driver raises the gate voltage to reach optimal R dson values. This driver is demonstrated on a 900-V SiC MOSFET that requires a 15 V onstate gate voltage to achieve optimum R dson . The device is switched at 50 V/ns in a 100-kHz, non-synchronous, 1:10, 300-W boost converter, with the power device switching 600 V and 5 A. It is shown that the gate voltage can be affected on a 100 ps scale, and that meaningful changes to fast power waveforms can be achieved.
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TL;DR: The effects of the driving frequency, pulse shape, strength of the applied electric field, and channel current, and the key factors that affect the sub-gap defect states are investigated, and a possible origin of the current degradation observed with an AC drive is suggested.
Abstract: Reliability issues associated with driving metal-oxide semiconductor thin film transistors (TFTs), which may arise from various sequential drain/gate pulse voltage stresses and/or certain environmental parameters, have not received much attention due to the competing desire to characterise the shift in the transistor characteristics caused by gate charging. In this paper, we report on the reliability of these devices under AC bias stress conditions because this is one of the major sources of failure. In our analysis, we investigate the effects of the driving frequency, pulse shape, strength of the applied electric field, and channel current, and the results are compared with those from a general reliability test in which the devices were subjected to negative/positive bias, temperature, and illumination stresses, which are known to cause the most stress to oxide semiconductor TFTs. We also report on the key factors that affect the sub-gap defect states, and suggest a possible origin of the current degradation observed with an AC drive. Circuit designers should apply a similar discovery and analysis method to ensure the reliable design of integrated circuits with oxide semiconductor devices, such as the gate driver circuits used in display devices.
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01 Aug 2017TL;DR: In this article, a Power Electronics Building Block (PEBB) based on 1.7 kV SiC MOSFET power modules is presented, which is an H-bridge converter module that can be cascaded to construct multilevel converters.
Abstract: This paper presents the design of a Power Electronics Building Block (PEBB) based on 1.7 kV SiC MOSFET power modules. The PEBB is an H-bridge converter module that can be cascaded to construct multilevel converters. Novel designs including gate driver with Rogowski shortcircuit protection, powerful distributed controller, isolated A/D sensor with high common-mode noise rejection, double-side cooling mechanical layout have been achieved. The paper begin with the evolution of PEBB architectures and the specifications of the designed PEBB. It then presents detailed design considerations and solutions of all the critical components. Finally, experimental results demonstrate the excellent performance of the individual components and the PEBB as a unity in various operation modes.
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TL;DR: In this article, a physics-based compact model for high-speed buffer layer insulated gate bipolar transistor (IGBT) is proposed, which utilizes the 1-D Fourier-based solution of ambipolar diffusion equation (ADE) implemented in MATLAB and Simulink.
Abstract: In this study, a physics-based compact model for high-speed buffer layer insulated gate bipolar transistor (IGBT) is proposed. The model utilizes the 1-D Fourier-based solution of ambipolar diffusion equation (ADE) implemented in MATLAB and Simulink. Based on the improved understanding on the inductive switching behavior of a high-speed buffer layer IGBT, the ADE is solved for all injection levels instead of high-level injection only as usually done. Assuming high-level injection condition in the buffer layer, the excess carrier transport, redistribution and recombination in the buffer layer are redescribed. Moreover, some physical characteristics such as the low conductivity of N-base at turn-on transient and free holes appeared in the depletion layer during turn-off process are also considered in the model. Finally, the double-pulse switching tests for a commercial field stop IGBT and a light punch-through carrier-stored trench bipolar transistor are used to validate the proposed model. The simulation results are compared with experiment results and good agreement is obtained.
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TL;DR: The proposed RGD circuit has achieved nearly 50% reduction in gate driver power consumption compared to the CGD circuit and can be modified appropriately to suit for insulated-gate bipolar transistors and other MOSFETs also.
Abstract: Silicon carbide (SiC) and gallium nitride metal–oxide–semiconductor field-effect transistors (MOSFETs) are capable of processing high power at high switching frequencies with less switching losses and conduction losses. The gate driver circuit power consumption is directly proportional to the switching frequency. The power taken from the gate supply is dissipated in the gate resistance of the conventional gate driver (CGD) circuit. Instead of dissipating all the gate driver energy, some energy can be recovered or recycled by utilizing the principle of resonance. This reduces the net power being taken from the gate supply. This paper presents a new resonant gate driver (RGD) circuit which consumes less power compared to the CGD circuit at high switching frequencies. The proposed gate driver is designed for SiC MOSFETs. It can be modified appropriately to suit for insulated-gate bipolar transistors and other MOSFETs also. The performance of the proposed circuit is simulated in LTSpice environment, and an experimental prototype of the proposed circuit is developed to validate its performance. The proposed RGD circuit has achieved nearly 50% reduction in gate driver power consumption compared to the CGD circuit.
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TL;DR: In this paper, high-speed gate drivers for Si IGBT and SiC MOSFET power modules of similar ratings of 1.2"kV/120"A have been designed.
Abstract: Silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET) is regarded as an attractive replacement for Si insulated gate bipolar transistor (IGBT) in high-power density applications due to its high switching speed and low switching loss. However, to fully utilise these benefits, the gate driver of the SiC MOSFET needs to be optimised to meet its special driving requirements. Fundamentally, both gate drivers for Si IGBT and SiC MOSFET share similar design methodology since these two power devices have the same MOS-gated structure. However, one of the major challenges in the gate driver design for SiC MOSFET is overcoming the electromagnetic interference, which is resulted from the much higher dv/dt and di/dt ratios during the switching transition. In this study, high-speed gate drivers for Si IGBT and SiC MOSFET power modules of similar ratings of 1.2 kV/120 A have been designed. The performances of gate driver have been experimentally evaluated by a double pulse test. The design considerations of gate driver to enable the replacement of Si IGBT by SiC MOSFET have been conclusively investigated and presented in this study.
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TL;DR: This paper demonstrates an integrated air-cooled three-phase SiC power block for industry applications that addresses key design aspects, such as high performance gate driver, low parasitic layout, optimized thermal management, as well as flexible control platform.
Abstract: Silicone carbide (SiC) power devices have been optimized in performance over the past decade. However, wide industry adoption of SiC technology still faces challenges from system design perspective. This paper demonstrates an integrated air-cooled three-phase SiC power block for industry applications. The key design aspects, such as high performance gate driver, low parasitic layout, optimized thermal management, as well as flexible control platform are addressed. Experimental results are provided to demonstrate the superior performance of the design.
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01 Sep 2017TL;DR: In this paper, the gate driver design challenges encountered due to fast switching transients in medium voltage half bridge silicon carbide MOSFET power modules are investigated and a reduced isolation capacitance regulated DC-DC power supply and a gate driver with an active Miller clamp circuit are presented.
Abstract: This paper investigates gate driver design challenges encountered due to the fast switching transients in medium voltage half bridge silicon carbide MOSFET power modules. The paper presents, design of a reduced isolation capacitance regulated DC-DC power supply and a gate driver with an active Miller clamp circuit for a 10 kV half bridge SiC MOSFET power module. Designed power supply and the gate driver circuit are verified in a double pulse test setup and a continuous switching operation using the 10 kV half bridge silicon carbide MOSFET power module. An in-depth experimental verification and detailed test results are presented to validate the gate driver functionality. The designed gate driver circuit shows satisfactory performance with increased common mode noise immunity and protection against the Miller current induced unwanted turn on.
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26 Mar 2017TL;DR: In this paper, an active gate driver (AGD) for switching control of the silicon carbide (SiC) MOSFETs is proposed, which improves the current and voltage profiles by suppression of the overshoot problems.
Abstract: This paper introduces a novel active gate driver (AGD) for switching control of the silicon carbide (SiC) MOSFETs The new gate driver improves the current and voltage profiles by suppression of the overshoot problems The main innovation of the proposed AGD is the modification of gate-source voltage slope in two stages for both turn-on and turn-off transitions with a simple closed-loop control, which directly implies to the control of di/dt and dv/dt The new gate driver is validated by experimental results Moreover, an analysis of performance and electromagnetic interference (EMI) is realized The experimental tests have been developed with 100 kHz of switching frequency and 200 V of dc-bus, in hard-switching conditions The results show that the proposed AGD can reduce EMI problems with a minimum side effect on the efficiency of the SiC MOSFETs
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TL;DR: In this article, a three-level gate driver for eGaN control HEMTs is proposed to minimize the reverse conduction time, which uses a wave-shape circuit designed by the HEMT rectifier mathematic model built with the MATLAB script, to compensate the IC propagation delay and obtain desired driving signal timing.
Abstract: Commercial eGaN HEMT gate drivers focus on high reliability to the strict gate driving voltage against parasitic components. However, they do not consider the high reverse conduction voltage due to the reverse conduction mechanism under ZVS condition. A three-level gate driver is proposed for eGaN control HEMTs. The midlevel voltage reduces the reverse conduction voltage since that the reverse conduction voltage decreases when gate voltage increases. The proposed driver is applied to a 7-MHz isolated resonant SEPIC converter. The efficiency was improved from 72.7% using conventional driver to 73.4% (an improvement of 0.7%) with 24-V input and 5-V/10-W output. An eGaN SR gate driver is proposed to minimize the reverse conduction time. The driver uses a wave-shape circuit, designed by the HEMT rectifier mathematic model built with the MATLAB script, to compensate the driving IC propagation delay and obtain desired driving signal timing. The proposed SR driver improves the efficiency from 79.9% without considering the driving IC delay to 84.7% (an improvement of 4.8%) with 18-V input and 5-V/10-W output.